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amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h 

Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11969
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Timothy Pearson 2015-06-01 20:35:42 -05:00 committed by Peter Stuge
parent 4e0d794039
commit 6ee6bdec25
1 changed files with 7 additions and 5 deletions
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12
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -1848,11 +1848,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
if (nv_DQSTrainCTL) {
mctHookBeforeAnyTraining(pMCTstat, pDCTstatA);
/* TODO: should be in mctHookBeforeAnyTraining */
_WRMSR(0x26C, 0x04040404, 0x04040404);
_WRMSR(0x26D, 0x04040404, 0x04040404);
_WRMSR(0x26E, 0x04040404, 0x04040404);
_WRMSR(0x26F, 0x04040404, 0x04040404);
if (!is_fam15h()) {
/* TODO: should be in mctHookBeforeAnyTraining */
_WRMSR(0x26C, 0x04040404, 0x04040404);
_WRMSR(0x26D, 0x04040404, 0x04040404);
_WRMSR(0x26E, 0x04040404, 0x04040404);
_WRMSR(0x26F, 0x04040404, 0x04040404);
}
mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass);
if (is_fam15h()) {