soc/intel/xeon_sp: Move PCH PCI device defines
Move the PCH PCI device defines out of the SOC specific PCI defines and into a common include. The PCH is common and doesn't need duplicate definitions. Change-Id: I1ca931e0f01e03c67f8f65ed7fd33c2c1d22183d Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Marc Jones
Marc Jones
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fe4c6b8d30
commit
6efc764c04
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@ -3,20 +3,10 @@
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#ifndef _SOC_PCI_DEVS_H_
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#define _SOC_PCI_DEVS_H_
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <types.h>
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
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#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
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#else
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#endif
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#include <soc/pch_pci_devs.h>
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#define SAD_ALL_DEV 29
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#define SAD_ALL_FUNC 0
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@ -132,47 +122,6 @@
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#define DEVICES_PER_IIO_STACK 4
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/* PCH Device info */
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#define XHCI_BUS_NUMBER 0x0
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#define PCH_DEV_SLOT_XHCI 0x14
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#define XHCI_FUNC_NUM 0x0
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
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#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
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#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
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#define HPET_BUS_NUM 0x0
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#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
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#define HPET0_FUNC_NUM 0x00
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#define PCH_IOAPIC_BUS_NUMBER 0xF0
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#define PCH_IOAPIC_DEV_NUM 0x1F
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#define PCH_IOAPIC_FUNC_NUM 0x00
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// ========== IOAPIC Definitions for DMAR/ACPI ========
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#define PCH_IOAPIC_ID 0x08
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// DMI3 B0D0F0 registers
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#define DMI3_DEVID 0x2020
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#define DMIRCBAR 0x50
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@ -0,0 +1,54 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_PCH_PCI_DEVS_H_
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#define _SOC_PCH_PCI_DEVS_H_
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if !defined(__SIMPLE_DEVICE__)
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#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
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#else
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#endif
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/* PCH Device info */
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#define XHCI_BUS_NUMBER 0x0
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#define PCH_DEV_SLOT_XHCI 0x14
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#define XHCI_FUNC_NUM 0x0
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
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#define HPET_BUS_NUM 0x0
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#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
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#define HPET0_FUNC_NUM 0x00
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
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#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
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#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
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#define PCH_IOAPIC_BUS_NUMBER 0xF0
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#define PCH_IOAPIC_DEV_NUM 0x1F
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#define PCH_IOAPIC_FUNC_NUM 0x00
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// ========== IOAPIC Definitions for DMAR/ACPI ========
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#define PCH_IOAPIC_ID 0x08
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#endif
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@ -4,8 +4,10 @@
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#define _SOC_PCI_DEVS_H_
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <hob_iiouds.h>
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#include <soc/pch_pci_devs.h>
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#define dump_csr(fmt, dev, reg) \
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printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
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@ -19,18 +21,6 @@
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((uint32_t)dev >> 12) & 0x07, #reg, reg, \
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pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg))
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
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#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
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#else
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#endif
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#define SAD_ALL_DEV 29
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#define SAD_ALL_FUNC 0
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#define SAD_ALL_PAM0123_CSR 0x40
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@ -118,19 +108,6 @@
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#define CHA_UTIL_ALL_FUNC 1
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#define CHA_UTIL_ALL_MMCFG_CSR 0xc0
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/* PCH Device info */
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#define XHCI_BUS_NUMBER 0x0
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#define PCH_DEV_SLOT_XHCI 0x14
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#define XHCI_FUNC_NUM 0x0
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
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#define HPET_BUS_NUM 0x0
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#define HPET_DEV_NUM PCH_DEV_SLOT_LPC
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#define HPET0_FUNC_NUM 0x00
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#define MMAP_VTD_CFG_REG_DEVID 0x2024
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#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034
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#define VTD_DEV_NUM 0x5
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@ -142,26 +119,6 @@
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#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
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#endif
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
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#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
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#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
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#define CBDMA_DEV_NUM 0x04
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#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function
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#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB
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@ -172,13 +129,6 @@
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#define APIC_DEV_NUM 0x05
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#define APIC_FUNC_NUM 0x00
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#define PCH_IOAPIC_BUS_NUMBER 0xF0
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#define PCH_IOAPIC_DEV_NUM 0x1F
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#define PCH_IOAPIC_FUNC_NUM 0x00
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// ========== IOAPIC Definitions for DMAR/ACPI ========
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#define PCH_IOAPIC_ID 0x08
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// DMI3 B0D0F0 registers
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#define DMI3_DEVID 0x2020
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#define DMIRCBAR 0x50
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