mainboard/hp/dl145_g1: Remove commented code
Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -62,51 +62,6 @@ unsigned long acpi_fill_madt(unsigned long current)
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}
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}
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/*
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int i;
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int j = 0;
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for(i = 1; i< sysconf.hc_possible_num; i++) {
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unsigned d = 0;
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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// 8131 need to use +4
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switch (sysconf.hcid[i]) {
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case 1:
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d = 7;
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break;
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case 3:
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d = 4;
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break;
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}
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switch (sysconf.hcid[i]) {
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case 1:
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case 3:
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dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
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res->base, gsi_base );
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gsi_base+=d;
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}
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}
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dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
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res->base, gsi_base );
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gsi_base+=d;
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}
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}
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break;
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}
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j++;
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}
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*/
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}
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@ -125,7 +125,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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setup_dl145g1_resource_map();
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//setup_default_resource_map();
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setup_coherent_ht_domain();
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wait_all_core0_started();
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@ -180,10 +179,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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for (i = RC0; i <= RC1; i <<= 1)
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change_i2c_mux(i);
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//dump_spd_registers(&sysinfo->ctrl[0]);
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//dump_spd_registers(&sysinfo->ctrl[1]);
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//dump_smbus_registers();
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allow_all_aps_stop(bsp_apicid);
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//It's the time to set ctrl now;
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