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google/fizz: Configure SATAXPCIe GPIOs to use native function 

BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that device detects SSD

Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Shelley Chen 2017-05-03 12:42:20 -07:00 committed by Duncan Laurie
parent d84c8f8601
commit 6f1bfaba8c
1 changed files with 4 additions and 3 deletions
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7
src/mainboard/google/fizz/gpio.h
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@ -143,9 +143,10 @@ static const struct pad_config gpio_table[] = {
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
PLTRST), /* H1_PCH_INT_ODL */
/* SATAXPCIE1 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* MB_PCIE_SATA#_DET */
/* SATAXPCIE2 */ PAD_CFG_GPI(GPP_E2, 20K_PU,
DEEP), /* DB_PCIE_SATA#_DET */
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
NF1), /* MB_PCIE_SATA#_DET */
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
NF1), /* DB_PCIE_SATA#_DET */
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */