From 6f1cb40ee6156c19be02e149dacfcf80401bc944 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 9 Jun 2021 22:11:12 +0530 Subject: [PATCH] soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function Align platform_fsp_silicon_init_params_cb() function implementation with romstage/fsp_params.c file platform_fsp_memory_init_params_cb() as: |- Override FSP-S Arch UPD(s) using arch_silicon_init_params(). |- Override FSP-S SoC UPDs using soc_silicon_init_params(). |- Override FSP-S Mainboard UPDs using mainboard_silicon_init_params(). TEST=FSP-S UPD dump shows no change without and with this code change. Change-Id: I4cf0b8423fb4038a7feddd97ff585027b3012605 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/55293 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/fsp_params.c | 29 +++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 0987b41bf2..605677b5c8 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -72,18 +72,14 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config * /* Override settings per board. */ } -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +static void soc_silicon_init_params(FSP_S_CONFIG *params, + struct soc_intel_alderlake_config *config) { int i; const struct microcode *microcode_file; size_t microcode_len; - FSP_S_CONFIG *params = &supd->FspsConfig; - FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd; uint32_t enable_mask; - struct soc_intel_alderlake_config *config; - config = config_of_soc(); mainboard_update_soc_chip_config(config); /* Parse device tree and enable/disable Serial I/O devices */ @@ -174,9 +170,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } - /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1; - /* Enable xDCI controller if enabled in devicetree and allowed */ if (!xdci_can_enable()) devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); @@ -273,7 +266,25 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Hwp = 1; params->Cx = 1; params->PsOnEnable = 1; +} +static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) +{ + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ + s_arch_cfg->EnableMultiPhaseSiliconInit = 1; +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + struct soc_intel_alderlake_config *config; + FSP_S_CONFIG *params = &supd->FspsConfig; + FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; + + config = config_of_soc(); + + arch_silicon_init_params(s_arch_cfg); + soc_silicon_init_params(params, config); mainboard_silicon_init_params(params); }