* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime. Signed-off-by: Aurelien Guillaume <aurelien@iwi.me> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Aurelien Guillaume
Patrick Georgi
parent
83628902ad
commit
6f22ecc2c9
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@ -3,6 +3,7 @@ choice
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depends on VENDOR_PC_ENGINES
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source "src/mainboard/pcengines/alix1c/Kconfig"
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source "src/mainboard/pcengines/alix2d3/Kconfig"
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endchoice
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@ -0,0 +1,31 @@
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config BOARD_PCENGINES_ALIX2D3
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bool "ALIX.2D3"
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select ARCH_X86
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select CPU_AMD_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select UDELAY_TSC
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select USE_DCACHE_RAM
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default pcengines/alix2d3
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depends on BOARD_PCENGINES_ALIX2D3
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config MAINBOARD_PART_NUMBER
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string
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default "ALIX.2D3"
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depends on BOARD_PCENGINES_ALIX2D3
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config IRQ_SLOT_COUNT
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int
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default 6
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depends on BOARD_PCENGINES_ALIX2D3
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config RAMBASE
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hex
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default 0x4000
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depends on BOARD_PCENGINES_ALIX2D3
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {
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int nothing;
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};
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -0,0 +1,46 @@
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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# How to get these? Boot linux and do this:
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# rdmsr 0x51400025
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register "lpc_serirq_enable" = "0x00001002"
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# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
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register "lpc_serirq_polarity" = "0x0000EFFD"
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# mode is high 10 bits (determined from code)
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register "lpc_serirq_mode" = "1"
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# Don't yet know how to find this.
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "1" # Wired on Alix.2D13 only
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)
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register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)
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register "unwanted_vpci[2]" = "0" # End of list has a zero
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device pci f.0 on end # ISA Bridge
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device pci f.1 on end # Flash controller
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device pci f.2 on end # IDE controller
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,114 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 10
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#define PIRQC 11
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#define PIRQD 9
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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/*
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* ALIX.2D3 interrupt wiring.
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*
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* Devices are:
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* 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
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* 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
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* 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
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* 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
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* 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
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* 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
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* 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
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* 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
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* 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
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* The only devices that interrupt are:
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*
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* What Device IRQ PIN PIN WIRED TO
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* -------------------------------------------------
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* AES 00:01.2 0a 01 A A
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* eth0 00:09.0 0b 01 A B
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* eth1 00:0a.0 0b 01 A C
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* eth2 00:0b.0 0b 01 A D
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* mpci 00:0c.0 0a 01 A A
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* mpci 00:0c.0 0b 02 B B
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* usb 00:0f.4 0b 04 D D
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* usb 00:0f.5 0b 04 D D
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*
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* The only swizzled interrupts are the ethernet controllers, where INTA is wired to
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* interrupt controller lines B, C and D.
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* Checksum */
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{
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/* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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/* CPU */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* On-board ethernet (Left) */
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{0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* On-board ethernet (Middle) */
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{0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* On-board ethernet (Right) */
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{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* Mini PCI (slot 1) */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,39 @@
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/*
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* This file is part of the coreboot project.
|
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*
|
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include "chip.h"
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static void init(struct device *dev)
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{
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printk(BIOS_DEBUG, "ALIX.2D3 ENTER %s\n", __func__);
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printk(BIOS_DEBUG, "ALIX.2D3 EXIT %s\n", __func__);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("PC Engines ALIX.2D3 Mainboard")
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.enable_dev = enable_dev,
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};
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|
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@ -0,0 +1,219 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
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#include <stdint.h>
|
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#include <stdlib.h>
|
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#include <spd.h>
|
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#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/hlt.h>
|
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#include <console/console.h>
|
||||
#include "lib/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
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|
||||
/* The ALIX.2D3 has no SMBus; the setup is hard-wired. */
|
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static void cs5536_enable_smbus(void)
|
||||
{
|
||||
}
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
|
||||
/* The part is a Hynix hy5du121622ctp-d43.
|
||||
*
|
||||
* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
|
||||
* Hynix
|
||||
* DDR SDRAM (5D)
|
||||
* VDD 2.5 VDDQ 2.5 (U)
|
||||
* 512M 8K REFRESH (12)
|
||||
* x16 (16)
|
||||
* 4banks (2)
|
||||
* SSTL_2 (2)
|
||||
* 4th GEN die (C)
|
||||
* Normal Power Consumption (<blank> )
|
||||
* TSOP (T)
|
||||
* Single Die (<blank>)
|
||||
* Lead Free (P)
|
||||
* DDR400 3-3-3 (D43)
|
||||
*/
|
||||
/* SPD array */
|
||||
static const u8 spdbytes[] = {
|
||||
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
|
||||
[SPD_BANK_DENSITY] = 0x40,
|
||||
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
|
||||
[SPD_MEMORY_TYPE] = 7,
|
||||
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
|
||||
[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
|
||||
[SPD_NUM_BANKS_PER_SDRAM] = 4,
|
||||
[SPD_PRIMARY_SDRAM_WIDTH] = 8,
|
||||
[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
|
||||
[SPD_NUM_COLUMNS] = 0xa,
|
||||
[SPD_NUM_ROWS] = 3,
|
||||
[SPD_REFRESH] = 0x3a,
|
||||
[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
|
||||
[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
|
||||
[SPD_tRAS] = 40,
|
||||
[SPD_tRCD] = 15,
|
||||
[SPD_tRFC] = 70,
|
||||
[SPD_tRP] = 15,
|
||||
[SPD_tRRD] = 10,
|
||||
};
|
||||
|
||||
static u8 spd_read_byte(u8 device, u8 address)
|
||||
{
|
||||
print_debug("spd_read_byte dev ");
|
||||
print_debug_hex8(device);
|
||||
|
||||
if (device != (0x50 << 1)) {
|
||||
print_debug(" returns 0xff\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
print_debug(" addr ");
|
||||
print_debug_hex8(address);
|
||||
print_debug(" returns ");
|
||||
print_debug_hex8(spdbytes[address]);
|
||||
print_debug("\n");
|
||||
|
||||
return spdbytes[address];
|
||||
}
|
||||
|
||||
#define ManualConf 0 /* Do automatic strapped PLL config */
|
||||
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
|
||||
#define PLLMSRlo 0x02000030
|
||||
|
||||
#define DIMM0 0xa0
|
||||
#define DIMM1 0xa2
|
||||
|
||||
#include "northbridge/amd/lx/raminit.h"
|
||||
#include "northbridge/amd/lx/pll_reset.c"
|
||||
#include "northbridge/amd/lx/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
/** Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/*
|
||||
* Disable power button, since it is hardwired to ground on this board,
|
||||
* and the power would be cut off atfer a 4-second delay otherwise.
|
||||
*/
|
||||
outl(0x00020000, PMS_IO_BASE + 0x40);
|
||||
|
||||
/*
|
||||
* Enable LEDs GPIO outputs to light up the leds
|
||||
* This is how the original tinyBIOS sets them after boot.
|
||||
* Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
|
||||
* may be used here, but not after PCI Init.
|
||||
* Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
|
||||
* leds-alix2.c driver. Coreboot dynamically assigns this space,
|
||||
* so the driver does not work anymore.
|
||||
* Good workaround: use the newer driver
|
||||
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
|
||||
* This resets the GPIO I/O space to 0x6100.
|
||||
* This may break other things, though.
|
||||
*/
|
||||
outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
|
||||
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
|
||||
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
|
||||
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
|
||||
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
|
||||
|
||||
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {0x50}},
|
||||
};
|
||||
|
||||
post_code(0x01);
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: Must do this AFTER cs5536_early_setup()!
|
||||
* It is counting on some early MSR setup for the CS5536.
|
||||
*/
|
||||
cs5536_setup_onchipuart(1);
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check memory */
|
||||
/* Enable this only if you are having questions. */
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
|
||||
/* Switch from Cache as RAM to real RAM.
|
||||
*
|
||||
* There are two ways we could think about this.
|
||||
*
|
||||
* 1. If we are using the romstage.inc ROMCC way, the stack is
|
||||
* going to be re-setup in the code following this code. Just
|
||||
* wbinvd the stack to clear the cache tags. We don't care
|
||||
* where the stack used to be.
|
||||
*
|
||||
* 2. This file is built as a normal .c -> .o and linked in
|
||||
* etc. The stack might be used to return etc. That means we
|
||||
* care about what is in the stack. If we are smart we set
|
||||
* the CAR stack to the same location as the rest of
|
||||
* coreboot. If that is the case we can just do a wbinvd.
|
||||
* The stack will be written into real RAM that is now setup
|
||||
* and we continue like nothing happened. If the stack is
|
||||
* located somewhere other than where LB would like it, you
|
||||
* need to write some code to do a copy from cache to RAM
|
||||
*
|
||||
* We use method 1 on Norwich and on this board too.
|
||||
*/
|
||||
post_code(0x02);
|
||||
print_err("POST 02\n");
|
||||
__asm__("wbinvd\n");
|
||||
print_err("Past wbinvd\n");
|
||||
|
||||
/* We are finding the return does not work on this board. Explicitly
|
||||
* call the label that is after the call to us. This is gross, but
|
||||
* sometimes at this level it is the only way out.
|
||||
*/
|
||||
void done_cache_as_ram_main(void);
|
||||
done_cache_as_ram_main();
|
||||
}
|
||||
|
||||
|
|
@ -739,7 +739,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
msr.lo |= (209 << 8); /* bits[15:8] = 209 */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
print_emerg("DRAM controller init done.\n");
|
||||
banner("DRAM controller init done.\n");
|
||||
post_code(POST_MEM_SETUP_GOOD); //0x7E
|
||||
|
||||
/* make sure there is nothing stale in the cache */
|
||||
|
|
|
|||
Loading…
Reference in New Issue