GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/cpu/x86: remove TSC_CALIBRATE_WITH_IO 

It's not selected by any path so it's a dead option with
associated dead code. Remove the config option as well as
the code paths that were never used any longer.

Change-Id: Ie536eee54e5c63bd90192f413c69e0dd2fea9171
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14299
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
This commit is contained in:
Aaron Durbin 2016-04-08 19:51:22 -05:00 committed by Martin Roth
parent b2229dc199
commit 6f3a55ae7e
2 changed files with 0 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/x86/Kconfig
View File

@ -48,12 +48,6 @@ config TSC_MONOTONIC_TIMER
help help
Expose monotonic time using the TSC. Expose monotonic time using the TSC.
# This option is used in code but never selected.
config TSC_CALIBRATE_WITH_IO
bool
depends on UDELAY_TSC
default n
# This option is used in code but never selected. # This option is used in code but never selected.
config UDELAY_TIMER2 config UDELAY_TIMER2
bool bool

58
src/cpu/x86/tsc/delay_tsc.c
View File

@ -16,7 +16,6 @@ static unsigned long calibrate_tsc(void)
return tsc_freq_mhz(); return tsc_freq_mhz();
} }
#else /* CONFIG_TSC_CONSTANT_RATE */ #else /* CONFIG_TSC_CONSTANT_RATE */
#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC ------- /* ------ Calibrate the TSC -------
@ -91,63 +90,6 @@ bad_ctc:
return 0; return 0;
} }
#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
/*
* this is the "no timer2" version.
* to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80
* then we read TSC again, and divide the difference by 1,000,000
* we have found on a wide range of machines that this gives us a a
* good microsecond value
* to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a
* 267 Mhz. p5, it gives us 1.1 microseconds.
* also, since gcc now supports long long, we use that.
* also no unsigned long long / operator, so we play games.
* about the only thing you can do with long longs, it seems,
*is return them and assign them.
* (and do asm on them, yuck)
* so avoid all ops on long longs.
*/
static unsigned long long calibrate_tsc(void)
{
unsigned long long start, end, delta;
unsigned long result, count;
printk(BIOS_SPEW, "Calibrating delay loop...\n");
start = rdtscll();
// no udivdi3 because we don't like libgcc. (only in x86emu)
// so we count to 1<< 20 and then right shift 20
for(count = 0; count < (1<<20); count ++)
inb(0x80);
end = rdtscll();
#if 0
// make delta be (endhigh - starthigh) + (endlow - startlow)
// but >> 20
// do it this way to avoid gcc warnings.
start = tsc_start.hi;
start <<= 32;
start |= start.lo;
end = tsc_end.hi;
end <<= 32;
end |= tsc_end.lo;
#endif
delta = end - start;
// at this point we have a delta for 1,000,000 outbs. Now rescale for one microsecond.
delta >>= 20;
// save this for microsecond timing.
result = delta;
printk(BIOS_SPEW, "end %llx, start %llx\n", end, start);
printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta);
printk(BIOS_SPEW, "%s 32-bit result is %ld\n",
__func__,
result);
return delta;
}
#endif /* CONFIG_TSC_CALIBRATE_WITH_IO */
#endif /* CONFIG_TSC_CONSTANT_RATE */ #endif /* CONFIG_TSC_CONSTANT_RATE */
void init_timer(void) void init_timer(void)