AGESA CIMX: Remove empty set_pcie_(de)reset

For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.

For amd/inagua, the defined function was actually initial
GPIO programming.

For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.

Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/amd/inagua/mainboard.c

@@ -20,21 +20,8 @@
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 
 void broadcom_init(void);
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
 
-/**
+static void init_gpios(void)
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
 {
 	/**
 	 * GPIO32 Pcie Device DeAssert for APU
@@ -48,7 +35,7 @@ void set_pcie_dereset(void)
 	 */
 
 	/* Multi-function pins switch to GPIO0-35, these pins are shared with
-	 * PCI pins, make sure Husson PCI device is disabled.
+	 * PCI pins, make sure Hudson PCI device is disabled.
 	 */
 	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
 
@@ -71,7 +58,7 @@ static void mainboard_enable(device_t dev)
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
 	/* Inagua mainboard specific setting */
-	set_pcie_dereset();
+	init_gpios();
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone

src/mainboard/amd/persimmon/mainboard.c

@@ -24,9 +24,6 @@
 #include <southbridge/amd/cimx/sb800/pci_devs.h>
 #include <northbridge/amd/agesa/family14/pci_devs.h>
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -121,23 +118,6 @@ static void pirq_setup(void)
 	picr_data_ptr = mainboard_picr_data;
 }
 
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/amd/south_station/mainboard.c

@@ -20,26 +20,6 @@
 #include <southbridge/amd/sb800/sb800.h>
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
 /**
  * Southstation using SB GPIO 17/18 to control the Red/Green LED
  * These two LEDs can be used to show the OS booting status.

src/mainboard/amd/torpedo/mainboard.c

@@ -19,25 +19,6 @@
 #define ONE_MB  0x100000
 //#define SMBUS_IO_BASE 0x6000
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
 
 /*************************************************
 * enable the dedicated function in torpedo board.

src/mainboard/amd/union_station/mainboard.c

@@ -19,26 +19,6 @@
 #include <southbridge/amd/sb800/sb800.h>
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/asrock/e350m1/mainboard.c

@@ -20,27 +20,6 @@
 #include <southbridge/amd/cimx/cimx_util.h>
 #include "SBPLATFORM.h"
 
-//#define SMBUS_IO_BASE 0x6000
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/elmex/pcm205400/mainboard.c

@@ -23,9 +23,6 @@
 #include <southbridge/amd/cimx/sb800/pci_devs.h>
 #include <northbridge/amd/agesa/family14/pci_devs.h>
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -120,23 +117,6 @@ static void pirq_setup(void)
 	picr_data_ptr = mainboard_picr_data;
 }
 
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/gizmosphere/gizmo/mainboard.c

@@ -23,26 +23,6 @@
 #include <southbridge/amd/sb800/sb800.h>
 #include "SBPLATFORM.h"
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/hp/abm/mainboard.c

@@ -21,9 +21,6 @@
 #include <southbridge/amd/agesa/hudson/pci_devs.h>
 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -92,16 +89,6 @@ static void pirq_setup(void)
 	picr_data_ptr = mainboard_picr_data;
 }
 
-/* TODO: mainboard specific SB AGESA callback */
-void set_pcie_reset(void)
-{
-}
-
-/* TODO: mainboard specific SB AGESA callback */
-void set_pcie_dereset(void)
-{
-}
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/jetway/nf81-t56n-lf/mainboard.c

@@ -26,9 +26,6 @@
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <northbridge/amd/agesa/family14/pci_devs.h>
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -123,23 +120,6 @@ static void pirq_setup(void)
 	picr_data_ptr = mainboard_picr_data;
 }
 
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/lippert/frontrunner-af/mainboard.c

@@ -111,26 +111,6 @@ static void init(struct device *dev)
 	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
 }
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/lippert/toucan-af/mainboard.c

@@ -77,26 +77,6 @@ static void init(struct device *dev)
 	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
 }
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/mainboard/pcengines/apu1/mainboard.c

@@ -30,9 +30,6 @@
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
 
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -176,22 +173,6 @@ static void config_addon_uart(void)
 		pnp_raw_resource(uart, 0xf2, 0x12);
 }
 
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/

src/southbridge/amd/cimx/sb700/late.c

@@ -31,15 +31,9 @@
 #include "sb700_cfg.h"                /* sb700 Cimx configuration */
 #include "chip.h"               /* struct southbridge_amd_cimx_sb700_config */
 
-
-/*implement in mainboard.c*/
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
 static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config
 static AMDSBCFG *sb_config = &sb_late_cfg;
 
-
 /**
  * @brief Entry point of Southbridge CIMx callout
  *

src/southbridge/amd/cimx/sb800/late.c

@@ -37,15 +37,9 @@
 #include "pci_devs.h"
 #include <southbridge/amd/common/amd_pci_util.h>
 
-/*implement in mainboard.c*/
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-
 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
 static AMDSBCFG *sb_config = &sb_late_cfg;
 
-
 /**
  * @brief Entry point of Southbridge CIMx callout
  *
@@ -62,11 +56,9 @@ static u32 sb800_callout_entry(u32 func, u32 data, void* config)
 	printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
 	switch (func) {
 	case CB_SBGPP_RESET_ASSERT:
-		set_pcie_reset();
 		break;
 
 	case CB_SBGPP_RESET_DEASSERT:
-		set_pcie_dereset();
 		break;
 
 	case IMC_FIRMWARE_FAIL:

src/southbridge/amd/cimx/sb900/late.c

@@ -28,14 +28,6 @@
 #include "SbPlatform.h" 	/* Platform Specific Definitions */
 #include "chip.h" 		/* struct southbridge_amd_cimx_sb900_config */
 
-
-/*implement in mainboard.c*/
-//void set_pcie_assert(void);
-//void set_pcie_deassert(void);
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-
 #ifndef _RAMSTAGE_
 #define _RAMSTAGE_
 #endif
@@ -60,13 +52,9 @@ u32 sb900_callout_entry(u32 func, u32 data, void* config)
 	printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n");
 	switch (func) {
 	case CB_SBGPP_RESET_ASSERT:
-		//set_pcie_assert();
-//-		set_pcie_reset();
 		break;
 
 	case CB_SBGPP_RESET_DEASSERT:
-		//set_pcie_deassert();
-//-		set_pcie_dereset();
 		break;
 
 //-	case IMC_FIRMWARE_FAIL: