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Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage. 

This is consistent with the device tree and the chip actually on the board.
Trivial.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jonathan Kollasch 2010-10-19 15:17:18 +00:00 committed by Jonathan A. Kollasch
parent 4e6f4cfa9c
commit 6f566b7a60
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/msi/ms7135/romstage.c
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@ -22,7 +22,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1)
/* Used by raminit. */
#define QRANK_DIMM_SUPPORT 1
@ -41,7 +41,7 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();