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Remove a couple of defines that seem to be the result of 

copy&paste, without actually being used.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-10-01 09:58:44 +00:00
parent e4bc0f6480
commit 6f56ad2d2e
10 changed files with 0 additions and 49 deletions
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6
src/mainboard/dell/s1850/romstage.c
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@ -20,9 +20,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
#define DEVPRES_CONFIG ( \
@ -35,9 +32,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);

3
src/mainboard/intel/eagleheights/romstage.c
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@ -59,9 +59,6 @@
#define UART_MSR 0x06
#define UART_SCR 0x07
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)

4
src/mainboard/intel/jarrell/romstage.c
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@ -29,10 +29,6 @@
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
/* Beta values: 0x00090800 */
/* Silver values: 0x000a0900 */
#define RECVENA_CONFIG 0x000a090a
#define RECVENB_CONFIG 0x000a090a
#define DIMM_MAP_LOGICAL 0x0124
static inline int spd_read_byte(unsigned device, unsigned address)

3
src/mainboard/intel/mtarvon/romstage.c
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@ -38,9 +38,6 @@
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)

3
src/mainboard/intel/truxton/romstage.c
View File

@ -40,9 +40,6 @@
#include "cpu/x86/bist.h"
#include "spd.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
static inline int spd_read_byte(u16 device, u8 address)

6
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -21,9 +21,6 @@
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -36,9 +33,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);

6
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -22,9 +22,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -37,9 +34,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);

6
src/mainboard/supermicro/x6dhe_g2/romstage.c
View File

@ -20,9 +20,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
@ -35,9 +32,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0708090a
#define RECVENB_CONFIG 0x0708090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);

6
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -20,9 +20,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -36,9 +33,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);

6
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -20,9 +20,6 @@
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -36,9 +33,6 @@
0 )
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
#define RECVENA_CONFIG 0x0808090a
#define RECVENB_CONFIG 0x0808090a
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);