src: Introduce `ARCH_ALL_STAGES_X86`

Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically
select the per-stage arch options. Subsequent commits will leverage
this to allow choosing between 32-bit and 64-bit coreboot where all
stages are x86. AMD Picasso and AMD Cezanne are the only exceptions
to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set
the per-stage arch options accordingly.

Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/arch/x86/Kconfig

@@ -28,6 +28,7 @@ config ARCH_RAMSTAGE_X86_32
 
 config ARCH_ALL_STAGES_X86_32
 	bool
+	default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
@@ -58,6 +59,10 @@ config ARCH_ALL_STAGES_X86_64
 	select ARCH_ROMSTAGE_X86_64
 	select ARCH_RAMSTAGE_X86_64
 
+config ARCH_ALL_STAGES_X86
+	bool
+	default y
+
 config ARCH_X86_64_PGTBL_LOC
 	hex "x86_64 page table location in CBFS"
 	depends on ARCH_BOOTBLOCK_X86_64

src/cpu/amd/agesa/Kconfig

@@ -6,7 +6,6 @@ config CPU_AMD_AGESA
 	default y if CPU_AMD_AGESA_FAMILY15_TN
 	default y if CPU_AMD_AGESA_FAMILY16_KB
 	default n
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE

src/cpu/amd/pi/Kconfig

@@ -4,7 +4,6 @@ config CPU_AMD_PI
 	bool
 	default y if CPU_AMD_PI_00730F01
 	default n
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE

src/cpu/intel/haswell/Kconfig

@@ -6,7 +6,6 @@ if CPU_INTEL_HASWELL
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX

src/cpu/intel/model_1067x/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_1067X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_106cx/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_106CX
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_2065x/Kconfig

@@ -5,7 +5,6 @@ if CPU_INTEL_MODEL_2065X
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select SSE2

src/cpu/intel/model_206ax/Kconfig

@@ -10,7 +10,6 @@ config ARCH_EXP_X86_64
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
 	select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
 	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES

src/cpu/intel/model_65x/Kconfig

@@ -1,5 +1,4 @@
 config CPU_INTEL_MODEL_65X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/intel/model_67x/Kconfig

@@ -1,5 +1,4 @@
 config CPU_INTEL_MODEL_67X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/intel/model_68x/Kconfig

@@ -2,6 +2,5 @@
 
 config CPU_INTEL_MODEL_68X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/intel/model_6bx/Kconfig

@@ -1,5 +1,4 @@
 config CPU_INTEL_MODEL_6BX
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/intel/model_6ex/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_6EX
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_6fx/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_6FX
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_6xx/Kconfig

@@ -1,5 +1,4 @@
 config CPU_INTEL_MODEL_6XX
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/intel/model_f2x/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_F2X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select SMM_ASEG

src/cpu/intel/model_f3x/Kconfig

@@ -1,6 +1,5 @@
 config CPU_INTEL_MODEL_F3X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON

src/cpu/intel/model_f4x/Kconfig

@@ -1,5 +1,4 @@
 config CPU_INTEL_MODEL_F4X
 	bool
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/cpu/qemu-x86/Kconfig

@@ -57,5 +57,4 @@ config CPU_QEMU_X86_32
 	bool
 	default n if CPU_QEMU_X86_64
 	default y
-	select ARCH_ALL_STAGES_X86_32
 endif

src/soc/amd/cezanne/Kconfig

@@ -70,6 +70,9 @@ config SOC_SPECIFIC_OPTIONS
 	select X86_AMD_FIXED_MTRRS
 	select X86_AMD_INIT_SIPI
 
+config ARCH_ALL_STAGES_X86
+	default n
+
 config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
 	default 5568
 

src/soc/amd/picasso/Kconfig

@@ -69,6 +69,9 @@ config CPU_SPECIFIC_OPTIONS
 	select UDK_2017_BINDING
 	select HAVE_CF9_RESET
 
+config ARCH_ALL_STAGES_X86
+	default n
+
 config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
 	default 3200
 

src/soc/amd/stoneyridge/Kconfig

@@ -10,7 +10,6 @@ if SOC_AMD_STONEYRIDGE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_SOC_NVS
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select COLLECT_TIMESTAMPS_NO_TSC

src/soc/example/min86/Kconfig

@@ -14,7 +14,6 @@ if SOC_EXAMPLE_MIN86
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select NO_MONOTONIC_TIMER
 	select NO_MMCONF_SUPPORT

src/soc/intel/alderlake/Kconfig

@@ -13,7 +13,6 @@ if SOC_INTEL_ALDERLAKE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/apollolake/Kconfig

@@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NO_PCAT_8259
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	# CPU specific options

src/soc/intel/baytrail/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_BAYTRAIL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES

src/soc/intel/braswell/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_BRASWELL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES

src/soc/intel/cannonlake/Kconfig

@@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NHLT
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/denverton_ns/Kconfig

@@ -13,7 +13,6 @@ config CPU_INTEL_NUM_FIT_ENTRIES
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select DEBUG_GPIO

src/soc/intel/elkhartlake/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_ELKHARTLAKE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/icelake/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_ICELAKE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/jasperlake/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_JASPERLAKE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/quark/Kconfig

@@ -9,7 +9,6 @@ if SOC_INTEL_QUARK
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select NO_MMCONF_SUPPORT
 	select REG_SCRIPT

src/soc/intel/skylake/Kconfig

@@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NHLT
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/tigerlake/Kconfig

@@ -8,7 +8,6 @@ if SOC_INTEL_TIGERLAKE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS

src/soc/intel/xeon_sp/Kconfig

@@ -26,7 +26,6 @@ if XEON_SP_COMMON_BASE
 
 config	CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CPU_INTEL_COMMON