mb/google/rex/var/screebo: Add initial devicetree config
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kun Liu
Lean Sheng Tan
parent
d5c1e13304
commit
6f6353d570
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@ -109,7 +109,7 @@ config OVERRIDE_DEVICETREE
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4 if BOARD_GOOGLE_REX0
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default 0x4 if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_SCREEBO
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -1,6 +1,346 @@
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chip soc/intel/meteorlake
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device domain 0 on
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end
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
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register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC1)"
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# Enable eDP in Port A
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register "ddi_port_A_config" = "1"
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# Enable HDMI in Port B
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register "ddi_port_B_config" = "0"
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# Enable Display Port Configuration
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_1] = DDI_ENABLE_HPD,
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[DDI_PORT_2] = DDI_ENABLE_HPD,
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[DDI_PORT_3] = DDI_ENABLE_HPD,
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[DDI_PORT_4] = DDI_ENABLE_HPD,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoPci,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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}"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Audio |
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#| I2C1 | Touchscreen |
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#| I2C3 | Touchpad |
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#| I2C4 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C5 | UFC |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[4] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 900,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DDR_SOC""
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register "options.tsr[1].desc" = ""Ambient""
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register "options.tsr[2].desc" = ""Charger""
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## Active Policy
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# FIXME: below values are initial reference values only
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register "policies.active" = "{
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[0] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(75, 90),
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TEMP_PCT(70, 80),
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TEMP_PCT(65, 70),
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TEMP_PCT(60, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(45, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(75, 90),
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TEMP_PCT(70, 80),
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TEMP_PCT(65, 70),
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TEMP_PCT(60, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(45, 30),
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}
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},
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[2] = {
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.target = DPTF_TEMP_SENSOR_2,
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.thresholds = {
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TEMP_PCT(75, 90),
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TEMP_PCT(70, 80),
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TEMP_PCT(65, 70),
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TEMP_PCT(60, 50),
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}
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}
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}"
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 15000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 57000,
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.max_power = 57000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref pcie_rp9 on
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# Enable SSD Card PCIE 9 using clk 4
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register "pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 4,
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.clk_req = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end # PCIE4_P9 SSD card
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device ref pcie_rp10 on
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# Enable SD Card PCIE4 rp10 using clk 7
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register "pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 7,
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.clk_req = 7,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
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register "srcclk_pin" = "7"
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device generic 0 on end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp2 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port4 on end
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end
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end
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end
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port2 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port4 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, CENTER, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, CENTER, ACPI_PLD_GROUP(3, 1))"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb3_port2 on end
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end
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end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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register "add_acpi_dma_property" = "true"
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register "enable_cnvi_ddr_rfim" = "true"
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device generic 0 on end
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end
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end
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device ref i2c4 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)"
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device i2c 50 on end
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end
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end
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device ref soc_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port4 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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end
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end
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