support HDT disassembly when cache as ram auto stage
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
72ee9b0ebe
commit
6f63c0297c
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@ -1,5 +1,6 @@
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/* by yhlu 6.2005 */
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/* We will use 4K bytes only */
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/* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/
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/* We may need 4K bytes only */
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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@ -12,9 +13,9 @@
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/*for normal part %ebx already contain cpu_init_detected from fallback call */
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cache_as_ram_setup:
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/* hope we can skip the double set for normal part */
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#if USE_FALLBACK_IMAGE == 1
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/* check if cpu_init_detected */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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@ -22,9 +23,6 @@ cache_as_ram_setup:
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movl %eax, %ebx /* We store the status */
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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xorl %eax, %eax
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xorl %edx, %edx
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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rdmsr
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@ -32,13 +30,6 @@ enable_fixed_mtrr_dram_modify:
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orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/*Clear all MTRRs */
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xorl %edx, %edx
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@ -55,12 +46,6 @@ clear_fixed_var_mtrr:
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* Enable the MTRRs and IORRs in SYSCFG */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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@ -69,31 +54,34 @@ clear_fixed_var_mtrr_out:
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wrmsr
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movl $0x269, %ecx
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wrmsr
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#endif
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#else
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#if CacheSize == 0x8000
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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#endif
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#else
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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#if CacheSize == 0x4000
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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#endif
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#if CacheSize == 0x2000
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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#endif
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#if CacheSize == 0x1000
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movl $0x06000000, %edx /* WB IO type */
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#endif
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#endif
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xorl %eax, %eax
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wrmsr
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#endif
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/* enable memory access for 0 - 1MB using top_mem */
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#endif
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/* enable memory access for first MBs using top_mem */
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movl $TOP_MEM, %ecx
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xorl %edx, %edx
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movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
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@ -101,7 +89,6 @@ clear_fixed_var_mtrr_out:
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#endif /* USE_FALLBACK_IMAGE == 1*/
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#if USE_FALLBACK_IMAGE == 0
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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@ -119,11 +106,26 @@ clear_fixed_var_mtrr_out:
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $0x0000000f, %edx /* AMD 40 bit */
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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#if USE_FALLBACK_IMAGE == 1
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/* Enable the MTRRs and IORRs in SYSCFG */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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#endif
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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@ -132,23 +134,22 @@ clear_fixed_var_mtrr_out:
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#if USE_FALLBACK_IMAGE == 1
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/* Read the range with lodsl*/
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movl $(CacheBase+CacheSize-4), %esi
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std
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cld
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $(CacheBase+CacheSize-4), %edi
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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#endif /*USE_FALLBACK_IMAGE == 1*/
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/* set up the stack pointer */
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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