diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index 49009ab0d1..c328eae91a 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -15,6 +15,6 @@
 void southbridge_smm_init(void);
 void southbridge_trigger_smi(void);
 void southbridge_clear_smi_status(void);
-void northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size);
+u32 northbridge_get_tseg_base(void);
 int cpu_get_apic_id_map(int *apic_id_map);
 void northbridge_write_smram(u8 smram);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 06b140ea0e..7e7f986ccf 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -114,22 +114,17 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	u32 tseg_size;
-	u32 tsegmb;
-	int phys_bits;
 	/* All range registers are aligned to 4KiB */
 	const u32 rmask = ~((1 << 12) - 1);
 
-	/* Some of the range registers are dependent on the number of physical
-	 * address bits supported. */
-	phys_bits = cpuid_eax(0x80000008) & 0xff;
-
-	/* The range bounded by the TSEGMB and BGSM registers encompasses the
-	 * SMRAM range as well as the IED range. However, the SMRAM available
-	 * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
-	 */
-	northbridge_get_tseg_base_and_size(&tsegmb, &tseg_size);
+	const u32 tsegmb = northbridge_get_tseg_base();
+	/* TSEG base is usually aligned down (to 8MiB). So we can't
+	   derive the TSEG size from the distance to GTT but use the
+	   configuration value instead. */
+	const u32 tseg_size = CONFIG_SMM_TSEG_SIZE;
 
+	/* The SMRAM available to the handler is 4MiB
+	   since the IEDRAM lives at TSEGMB + 4MiB. */
 	params->smram_base = tsegmb;
 	params->smram_size = 4 << 20;
 	params->ied_base = tsegmb + params->smram_size;
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index 99d8fbbcf4..50615b5f2d 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -325,16 +325,11 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
 	return value;
 }
 
-void
-northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+u32 northbridge_get_tseg_base(void)
 {
-	device_t dev;
-	u32 bgsm;
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 
-	*tsegmb = northbridge_get_base_reg(dev, TSEG);
-	bgsm = northbridge_get_base_reg(dev, BGSM);
-	*tseg_size = bgsm - *tsegmb;
+	return northbridge_get_base_reg(dev, TSEG);
 }
 
 void northbridge_write_smram(u8 smram)
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 7f44272593..06c0a9655b 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -162,16 +162,11 @@ static void mc_read_resources(device_t dev)
 	add_fixed_resources(dev, 10);
 }
 
-void
-northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+u32 northbridge_get_tseg_base(void)
 {
-	device_t dev;
-	u32 bgsm;
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 
-	*tsegmb = pci_read_config32(dev, TSEG) & ~1;
-	bgsm = pci_read_config32(dev, D0F0_GTT_BASE);
-	*tseg_size = bgsm - *tsegmb;
+	return pci_read_config32(dev, TSEG) & ~1;
 }
 
 static void mc_set_resources(device_t dev)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 53d93a2501..a67b84ddf4 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -500,16 +500,11 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
 	return value;
 }
 
-void
-northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+u32 northbridge_get_tseg_base(void)
 {
-	device_t dev;
-	u32 bgsm;
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 
-	*tsegmb = northbridge_get_base_reg(dev, TSEG);
-	bgsm = northbridge_get_base_reg(dev, BGSM);
-	*tseg_size = bgsm - *tsegmb;
+	return northbridge_get_base_reg(dev, TSEG);
 }
 
 void northbridge_write_smram(u8 smram)