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vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h 

Update the file to match the QuarkFsp code.

TEST=Build and run on Galileo Gen2

Change-Id: I090578d32165d34863548aec0e4a38fe915683c6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14452
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-03-11 07:55:55 -08:00 committed by Leroy P Leahy
parent 36d7418afa
commit 6f94c5d41a
1 changed files with 28 additions and 34 deletions
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62
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
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@ -36,18 +36,20 @@ are permitted provided that the following conditions are met:
#pragma pack(1) #pragma pack(1)
// /** TODO - Port to fit Quark SoC.
// TODO - Port to fit Quark SoC. **/
//
#define MAX_CHANNELS_NUM 2 #define MAX_CHANNELS_NUM 1
#define MAX_DIMMS_NUM 2 #define MAX_DIMMS_NUM 1
typedef struct { typedef struct {
UINT8 DimmId; UINT8 DimmId;
UINT32 SizeInMb; UINT32 SizeInMb;
UINT16 MfgId; UINT16 MfgId;
UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ /** Module part number for DDR3 is 18 bytes however for
DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
**/
UINT8 ModulePartNum[20];
} DIMM_INFO; } DIMM_INFO;
typedef struct { typedef struct {
@ -80,33 +82,34 @@ typedef struct {
UINT64 Signature; UINT64 Signature;
/** Offset 0x0028 /** Offset 0x0028
**/ **/
UINT8 Revision; UINT64 Revision;
/** Offset 0x0029 /** Offset 0x0030
Tseg Size **/
Size of SMRAM memory reserved. UINT32 PcdRmuBinaryBaseAddress;
/** Offset 0x0034
**/
UINT32 PcdRmuBinaryLen;
/** Offset 0x0038
**/ **/
UINT8 PcdSmmTsegSize; UINT8 PcdSmmTsegSize;
/** Offset 0x002A /** Offset 0x0039
**/ **/
UINT32 PcdPlatformDataBaseAddress; UINT8 PcdPlatformType;
/** Offset 0x002E /** Offset 0x003A
**/ **/
UINT32 PcdPlatformDataMaxLen; UINT8 ReservedMemoryInitUpd[22];
/** Offset 0x0032
**/
UINT8 ReservedMemoryInitUpd[14];
} MEMORY_INIT_UPD; } MEMORY_INIT_UPD;
typedef struct { typedef struct {
/** Offset 0x0040 /** Offset 0x0050
**/ **/
UINT64 Signature; UINT64 Signature;
/** Offset 0x0048 /** Offset 0x0058
**/ **/
UINT8 Revision; UINT64 Revision;
/** Offset 0x0049 /** Offset 0x0060
**/ **/
UINT8 ReservedSiliconInitUpd[183]; UINT8 ReservedSiliconInitUpd[32];
} SILICON_INIT_UPD; } SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ #define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
@ -119,10 +122,7 @@ typedef struct _UPD_DATA_REGION {
UINT64 Signature; UINT64 Signature;
/** Offset 0x0008 /** Offset 0x0008
**/ **/
UINT8 Revision; UINT64 Revision;
/** Offset 0x0009
**/
UINT8 ReservedUpd0[7];
/** Offset 0x0010 /** Offset 0x0010
**/ **/
UINT32 MemoryInitUpdOffset; UINT32 MemoryInitUpdOffset;
@ -135,10 +135,10 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x0020 /** Offset 0x0020
**/ **/
MEMORY_INIT_UPD MemoryInitUpd; MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0040 /** Offset 0x0050
**/ **/
SILICON_INIT_UPD SiliconInitUpd; SILICON_INIT_UPD SiliconInitUpd;
/** Offset 0x0100 /** Offset 0x0080
**/ **/
UINT16 PcdRegionTerminator; UINT16 PcdRegionTerminator;
} UPD_DATA_REGION; } UPD_DATA_REGION;
@ -157,12 +157,6 @@ typedef struct _VPD_DATA_REGION {
/** Offset 0x000C /** Offset 0x000C
**/ **/
UINT32 PcdUpdRegionOffset; UINT32 PcdUpdRegionOffset;
/** Offset 0x0010
**/
UINT8 UnusedVpdSpace0[16];
/** Offset 0x0020
**/
UINT32 PcdFspReservedMemoryLength;
} VPD_DATA_REGION; } VPD_DATA_REGION;
#pragma pack() #pragma pack()