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mb/google/brya/var/agah: Explictly program the dGPU's PCI IRQ 

Currently the `pch_pirq_init()` function in lpc_lib.c will program
PIRQ IRQs for all PCI devices discovered during enumeration. This
may not be correct for all devices, and causes strange behavior
with the Nvidia dGPU; it will start out with IRQ 11 and then after
a suspend/resume cycle, it will get programmed back to 16, so the
Linux kernel must be doing some IRQ sanitization at some point.
To fix this anomaly, explicitly program the IRQ to 16 (which we
know is what IRQ it will eventually take).

BUG=b:243972575
TEST=`lspci -vvv -s1:00.0|grep IRQ` shows IRQ 16 is programmed
at boot and stays consistent after suspend/resume.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I66ca3701c4c2fe5359621023b1fd45f8afd3b745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67746
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2022-09-20 11:48:40 -06:00 committed by Paul Fagerburg
parent 0eba73228f
commit 6f95cb50c5
1 changed files with 17 additions and 1 deletions
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18
src/mainboard/google/brya/variants/agah/variant.c
View File

@ -5,7 +5,7 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <delay.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <gpio.h>
#include <timer.h>
#include <types.h>
@ -161,3 +161,19 @@ void variant_fill_ssdt(const struct device *dev)
acpigen_write_method_end();
acpigen_write_scope_end();
}
void variant_finalize(void)
{
/*
* Currently the `pch_pirq_init()` function in lpc_lib.c will program
* PIRQ IRQs for all PCI devices discovered during enumeration. This may
* not be correct for all devices, and causes strange behavior with the
* Nvidia dGPU; it will start out with IRQ 11 and then after a
* suspend/resume cycle, it will get programmed back to 16, so the Linux
* kernel must be doing some IRQ sanitization at some point. To fix
* this anomaly, explicitly program the IRQ to 16 (which we know is what
* IRQ it will eventually take).
*/
const struct device *dgpu = DEV_PTR(dgpu);
pci_write_config8(dgpu, PCI_INTERRUPT_LINE, 16);
}