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soc/amd/common/block/lpc/espi_util: use [read,write][8,16,32]p 

Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c6f5c73b41546b304f16994d517ed15dbb555f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Felix Held 2022-09-29 16:13:26 +02:00
parent 25866fe893
commit 6f9e817bbf
1 changed files with 7 additions and 7 deletions
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14
src/soc/amd/common/block/lpc/espi_util.c
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@ -3,7 +3,7 @@
#include <amdblocks/chip.h>
#include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <arch/mmio.h>
#include <device/mmio.h>
#include <console/console.h>
#include <espi.h>
#include <soc/pci_devs.h>
@ -32,32 +32,32 @@ static uintptr_t espi_get_bar(void)
static uint32_t espi_read32(unsigned int reg)
{
return read32((void *)(espi_get_bar() + reg));
return read32p(espi_get_bar() + reg);
}
static void espi_write32(unsigned int reg, uint32_t val)
{
write32((void *)(espi_get_bar() + reg), val);
write32p(espi_get_bar() + reg, val);
}
static uint16_t espi_read16(unsigned int reg)
{
return read16((void *)(espi_get_bar() + reg));
return read16p(espi_get_bar() + reg);
}
static void espi_write16(unsigned int reg, uint16_t val)
{
write16((void *)(espi_get_bar() + reg), val);
write16p(espi_get_bar() + reg, val);
}
static uint8_t espi_read8(unsigned int reg)
{
return read8((void *)(espi_get_bar() + reg));
return read8p(espi_get_bar() + reg);
}
static void espi_write8(unsigned int reg, uint8_t val)
{
write8((void *)(espi_get_bar() + reg), val);
write8p(espi_get_bar() + reg, val);
}
static inline uint32_t espi_decode_io_range_en_bit(unsigned int idx)