peppy: Update GPIO table + USB port map.

- Update GPIO table to match board.
- Update USB port map.
- Remove iSSD power sequencing code.

Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710
Reviewed-on: https://gerrit.chromium.org/gerrit/56869
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/mainboard/google/peppy/gpio.h

@@ -39,8 +39,8 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
 	LP_GPIO_INPUT,         /* 13: RAM_ID0 */
 	LP_GPIO_INPUT,         /* 14: EC_IN_RW */
 	LP_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
-	LP_GPIO_OUT_LOW,       /* 16: PCH_SSD_12_EN (iSSD VDDC) */
+	LP_GPIO_UNUSED,        /* 16: UNUSED */
-	LP_GPIO_OUT_LOW,       /* 17: PCH_SSD_18_EN (iSSD VCCQ) */
+	LP_GPIO_UNUSED,        /* 17: UNUSED */
 	LP_GPIO_NATIVE,        /* 18: PCIE_CLKREQ_WLAN# */
 	LP_GPIO_UNUSED,        /* 19: UNUSED */
 	LP_GPIO_UNUSED,        /* 20: UNUSED */
@@ -56,7 +56,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
 	LP_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
 	LP_GPIO_NATIVE,        /* 31: NATIVE: ACPRESENT */
 	LP_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
-	LP_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	LP_GPIO_UNUSED,        /* 33: UNUSED */
 	LP_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
 	LP_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
 	LP_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
@@ -67,12 +67,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
 	LP_GPIO_UNUSED,        /* 41: UNUSED */
 	LP_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
 	LP_GPIO_UNUSED,        /* 43: UNUSED */
-	LP_GPIO_OUT_LOW,       /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */
+	LP_GPIO_OUT_HIGH,      /* 44: PP3300_SSD_EN */
 	LP_GPIO_OUT_HIGH,      /* 45: PP3300_CODEC_EN */
 	LP_GPIO_OUT_HIGH,      /* 46: WLAN_DISABLE_L */
 	LP_GPIO_INPUT,         /* 47: RAM_ID2 */
 	LP_GPIO_UNUSED,        /* 48: UNUSED */
-	LP_GPIO_OUT_LOW,       /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */
+	LP_GPIO_UNUSED,        /* 49: UNUSED */
 	LP_GPIO_UNUSED,        /* 50: UNUSED */
 	LP_GPIO_INPUT,         /* 51: ALS_INT_L */
 	LP_GPIO_INPUT,         /* 52: SIM_DET */
@@ -84,12 +84,12 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
 	LP_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
 	LP_GPIO_OUT_HIGH,      /* 59: LTE_DISABLE_L */
 	LP_GPIO_NATIVE,        /* 60: NATIVE: SML0ALERT */
-	LP_GPIO_NATIVE,        /* 61: NATIVE: PCH_SUS_STAT */
+	LP_GPIO_UNUSED,        /* 61: UNUSED */
-	LP_GPIO_NATIVE,        /* 62: NATIVE: PCH_SUS_CLK */
+	LP_GPIO_UNUSED,        /* 62: UNUSED */
 	LP_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
 	LP_GPIO_UNUSED,        /* 64: UNUSED */
 	LP_GPIO_UNUSED,        /* 65: UNUSED */
-	LP_GPIO_UNUSED,        /* 66: UNUSED */
+	LP_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
 	LP_GPIO_UNUSED,        /* 67: UNUSED */
 	LP_GPIO_UNUSED,        /* 68: UNUSED */
 	LP_GPIO_UNUSED,        /* 69: UNUSED */

src/mainboard/google/peppy/romstage.c

@@ -98,39 +98,6 @@ static void copy_spd(struct pei_data *peid)
 	       sizeof(peid->spd_data[0]));
 }
 
-/*
- * Power Sequencing for SanDisk i100/i110 SSD
- *
- * Must be sequenced in this order with specified timing.
- *
- * 1. VCC_IO    : 30us - 100ms
- * 2. VCC_FLASH : 70us - 10ms
- * 3. VCCQ      : 70us - 10ms
- * 4. VDDC      : 30us - 100ms
- *
- * There is no feedback to know if the voltage has stabilized
- * so this implementation will use the max ramp times.  That
- * means it adds significantly to the boot time.
- */
-static void issd_power_sequence(void)
-{
-	struct gpio_seq {
-		int gpio;
-		int wait_ms;
-	} issd_gpio_seq[] = {
-		{ 49, 100 },	/* VCC_IO:    GPIO 49, wait 100ms */
-		{ 44, 10 },	/* VCC_FLASH: GPIO 44, wait 10ms */
-		{ 17, 10 },	/* VCCQ:      GPIO 17, wait 10ms */
-		{ 16, 100 },	/* VDDC:      GPIO 16, wait 100ms */
-	};
-	int step;
-
-	for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) {
-		set_gpio(issd_gpio_seq[step].gpio, 1);
-		udelay(issd_gpio_seq[step].wait_ms * 1000);
-	}
-}
-
 void mainboard_romstage_entry(unsigned long bist)
 {
 	struct pei_data pei_data = {
@@ -161,18 +128,18 @@ void mainboard_romstage_entry(unsigned long bist)
 		usb2_ports: {
 			/* Length, Enable, OCn# */
 			{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
-			{ 0x0040, 1, 0               }, /* P1: Port A, CN10 */
+			{ 0x0040, 1, 0               }, /* P1: Port A */
 			{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
 			{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
-			{ 0x0040, 1, 2               }, /* P4: Port B, CN6  */
+			{ 0x0040, 1, 2               }, /* P4: USB 2.0 Port */
-			{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */
+			{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */
 			{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
 			{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
 		},
 		usb3_ports: {
 			/* Enable, OCn# */
-			{ 1, 0               }, /* P1; Port A, CN10 */
+			{ 1, 0               }, /* P1; Port A, CN6 */
-			{ 1, 2               }, /* P2; Port B, CN6  */
+			{ 0, USB_OC_PIN_SKIP }, /* P2; */
 			{ 0, USB_OC_PIN_SKIP }, /* P3; */
 			{ 0, USB_OC_PIN_SKIP }, /* P4; */
 		},
@@ -188,7 +155,4 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	/* Call into the real romstage main with this board's attributes. */
 	romstage_common(&romstage_params);
-
-	/* Power sequence the iSSD module */
-	issd_power_sequence();
 }