diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 5f3f0ee858..b5e753d222 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -327,4 +327,13 @@ void hudson_read_mode(u32 mode)
 					& ~SPI_READ_MODE_MASK) | mode);
 }
 
+void hudson_tpm_decode_spi(void)
+{
+	device_t dev = PCI_DEV(0, 0x14, 3);	/* LPC device */
+
+	u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
+							| ROUTE_TPM_2_SPI);
+}
+
 #endif
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 6b6343bc10..baed2c30ad 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -69,6 +69,7 @@
 #define REV_HUDSON_A12			0x12
 
 #define SPIROM_BASE_ADDRESS_REGISTER	0xA0
+#define   ROUTE_TPM_2_SPI		BIT(3)
 #define   SPI_ROM_ENABLE		0x02
 #define   SPI_BASE_ADDRESS		0xFEC10000
 
@@ -188,8 +189,7 @@ void hudson_disable_4dw_burst(void);
 void hudson_set_readspeed(u16 norm, u16 fast);
 void lpc_wideio_512_window(uint16_t base);
 void lpc_wideio_16_window(uint16_t base);
-
-
+void hudson_tpm_decode_spi(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #if IS_ENABLED(CONFIG_HUDSON_UART)
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index d73979cd97..60a1b88bae 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -126,10 +126,13 @@ static void hudson_lpc_read_resources(device_t dev)
 static void hudson_lpc_set_resources(struct device *dev)
 {
 	struct resource *res;
+	u32 spi_enable_bits;
 
-	/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
+	/* Special case. The SpiRomEnable and other enables should STAY set. */
 	res = find_resource(dev, 2);
-	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
+	spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+	spi_enable_bits &= 0xF;
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
 
 	pci_dev_set_resources(dev);
 }