vc/amd/opensil: add openSIL stub implementation

Add a stub implementation of the openSIL interface between coreboot and
vendorcode. This can be used to add most of the coreboot-side support
for a SoC using openSIL without the actual opnSIL code already being
publicly available. Once the corresponding openSIL code is available,
the SoC can then switch over to using the actual openSIL implementation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/vendorcode/amd/opensil/Kconfig

@@ -2,6 +2,13 @@
 
 if SOC_AMD_OPENSIL
 
+config SOC_AMD_OPENSIL_STUB
+	bool
+	help
+	  Select this option to include the openSIL stub in the build that can
+	  be used for build-testing before the actual openSIL source code for a
+	  SoC is released.
+
 config SOC_AMD_OPENSIL_GENOA_POC
 	bool
 	help

src/vendorcode/amd/opensil/Makefile.mk

@@ -2,6 +2,12 @@
 
 ifeq ($(CONFIG_SOC_AMD_OPENSIL),y)
 
+ifeq ($(CONFIG_SOC_AMD_OPENSIL_STUB),y)
+
+subdirs-y += stub
+
+else # CONFIG_SOC_AMD_OPENSIL_STUB
+
 ifneq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y)
     $(error OpenSIL can only be built for either x86 or x86_64)
 endif
@@ -90,4 +96,6 @@ $(OBJPATH)/opensil.a: $(OBJPATH)/opensil/lib$(opensil_target_name).a
 romstage-libs += $(OBJPATH)/opensil.a
 ramstage-libs += $(OBJPATH)/opensil.a
 
-endif
+endif # CONFIG_SOC_AMD_OPENSIL_STUB
+
+endif # CONFIG_SOC_AMD_OPENSIL

src/vendorcode/amd/opensil/stub/Makefile.mk

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c

src/vendorcode/amd/opensil/stub/opensil.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _OPENSIL_H_
+#define _OPENSIL_H_
+
+#include <acpi/acpi.h>
+
+// Add the memory map to dev, starting at index idx, returns last use idx
+void add_opensil_memmap(struct device *dev, unsigned long *idx);
+// Fill in FADT from openSIL
+void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
+
+void setup_opensil(void);
+void opensil_xSIM_timepoint_1(void);
+void opensil_xSIM_timepoint_2(void);
+void opensil_xSIM_timepoint_3(void);
+
+#endif

src/vendorcode/amd/opensil/stub/ramstage.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <device/device.h>
+#include "opensil.h"
+
+void add_opensil_memmap(struct device *dev, unsigned long *idx)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void setup_opensil(void)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_1(void)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+	printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}

src/vendorcode/amd/opensil/stub/romstage.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <inttypes.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	/* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to
+	   call, we just use 0xc0000000 here which should be a usable value in most cases */
+	uintptr_t top_mem = 0xc0000000;
+
+	printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem);
+
+	/* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so
+	   account for potentially ill aligned TOP_MEM. */
+	if (CONFIG_SMM_TSEG_SIZE) {
+		top_mem -= CONFIG_SMM_TSEG_SIZE;
+		top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
+	}
+
+	return top_mem;
+}