google/banon: add new board as variant of cyan baseboard
Add support for google/banon (Acer Chromebook 15 CB3-531) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new banon variant Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
2f7813f7b3
commit
6fd2e0e088
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@ -41,6 +41,7 @@ config MAINBOARD_FAMILY
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config VARIANT_DIR
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string
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default "banon" if BOARD_GOOGLE_BANON
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default "cyan" if BOARD_GOOGLE_CYAN
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default "edgar" if BOARD_GOOGLE_EDGAR
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default "reks" if BOARD_GOOGLE_REKS
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@ -48,6 +49,7 @@ config VARIANT_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "Banon" if BOARD_GOOGLE_BANON
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default "Cyan" if BOARD_GOOGLE_CYAN
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default "Edgar" if BOARD_GOOGLE_EDGAR
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default "Reks" if BOARD_GOOGLE_REKS
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@ -59,6 +61,7 @@ config MAINBOARD_VENDOR
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config DEVICETREE
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string
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default "variants/banon/devicetree.cb" if BOARD_GOOGLE_BANON
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default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN
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default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR
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default "variants/reks/devicetree.cb" if BOARD_GOOGLE_REKS
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@ -84,6 +87,7 @@ config VGA_BIOS_ID
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config GBB_HWID
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string
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depends on CHROMEOS
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default "BANON TEST A-A 8050" if BOARD_GOOGLE_BANON
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default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN
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default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR
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default "REKS TEST A-A 3004" if BOARD_GOOGLE_REKS
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@ -1,3 +1,7 @@
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config BOARD_GOOGLE_BANON
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bool "Banon"
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select BOARD_GOOGLE_BASEBOARD_CYAN
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config BOARD_GOOGLE_CYAN
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bool "Cyan"
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select BOARD_GOOGLE_BASEBOARD_CYAN
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@ -0,0 +1,42 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2015 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += romstage.c
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romstage-y += spd_util.c
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ramstage-y += gpio.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF
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SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF
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SPD_SOURCES += empty
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SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD
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SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Banon
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,150 @@
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chip soc/intel/braswell
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############################################################
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# Set the parameters for MemoryInit
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############################################################
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register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
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register "PcdMrcInitMmioSize" = "0x0800"
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register "PcdMrcInitSpdAddr1" = "0xa0"
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register "PcdMrcInitSpdAddr2" = "0xa2"
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register "PcdIgdDvmt50PreAlloc" = "1"
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register "PcdApertureSize" = "2"
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register "PcdGttSize" = "1"
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register "PcdDvfsEnable" = "1"
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register "PcdCaMirrorEn" = "1"
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############################################################
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# Set the parameters for SiliconInit
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############################################################
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register "PcdSdcardMode" = "PCH_ACPI_MODE"
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register "PcdEnableHsuart0" = "0"
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register "PcdEnableHsuart1" = "1"
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register "PcdEnableAzalia" = "1"
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register "PcdEnableXhci" = "1"
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register "PcdEnableLpe" = "1"
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register "PcdEnableDma0" = "1"
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register "PcdEnableDma1" = "1"
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register "PcdEnableI2C0" = "0"
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register "PcdEnableI2C1" = "1"
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register "PcdEnableI2C2" = "0"
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register "PcdEnableI2C3" = "0"
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register "PcdEnableI2C4" = "1"
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register "PcdEnableI2C5" = "1"
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register "PcdEnableI2C6" = "0"
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register "PunitPwrConfigDisable" = "0" # Enable SVID
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register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
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register "PcdEmmcMode" = "PCH_ACPI_MODE"
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register "PcdUsb3ClkSsc" = "1"
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register "PcdDispClkSsc" = "1"
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register "PcdSataClkSsc" = "1"
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register "PcdEnableSata" = "0" # Disable SATA
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register "Usb2Port0PerPortPeTxiSet" = "7"
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register "Usb2Port0PerPortTxiSet" = "6"
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register "Usb2Port0IUsbTxEmphasisEn" = "3"
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register "Usb2Port0PerPortTxPeHalf" = "1"
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register "Usb2Port1PerPortPeTxiSet" = "7"
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register "Usb2Port1PerPortTxiSet" = "6"
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register "Usb2Port1IUsbTxEmphasisEn" = "3"
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register "Usb2Port1PerPortTxPeHalf" = "1"
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register "Usb2Port2PerPortPeTxiSet" = "7"
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register "Usb2Port2PerPortTxiSet" = "6"
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register "Usb2Port2IUsbTxEmphasisEn" = "3"
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register "Usb2Port2PerPortTxPeHalf" = "1"
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register "Usb2Port3PerPortPeTxiSet" = "7"
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register "Usb2Port3PerPortTxiSet" = "6"
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register "Usb2Port3IUsbTxEmphasisEn" = "3"
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register "Usb2Port3PerPortTxPeHalf" = "1"
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register "Usb2Port4PerPortPeTxiSet" = "7"
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register "Usb2Port4PerPortTxiSet" = "6"
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register "Usb2Port4IUsbTxEmphasisEn" = "3"
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register "Usb2Port4PerPortTxPeHalf" = "1"
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register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
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register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
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register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
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register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
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register "PcdSataInterfaceSpeed" = "3"
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register "PcdPchSsicEnable" = "1"
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register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
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register "PMIC_I2CBus" = "1"
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register "ISPEnable" = "0" # Disable IUNIT
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register "ISPPciDevConfig" = "3"
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register "PcdSdDetectChk" = "0" # Disable SD card detect
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register "I2C0Frequency" = "1"
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register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
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register "I2C2Frequency" = "1"
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register "I2C3Frequency" = "1"
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register "I2C4Frequency" = "1"
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register "I2C5Frequency" = "1"
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register "I2C6Frequency" = "1"
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# LPE audio codec settings
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register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
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# Enable devices in ACPI mode
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register "lpss_acpi_mode" = "1"
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register "emmc_acpi_mode" = "1"
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register "sd_acpi_mode" = "1"
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register "lpe_acpi_mode" = "1"
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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# Allow PCIe devices to wake system from suspend
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register "pcie_wake_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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# EDS Table 24-4, Figure 24-5
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device pci 00.0 on end # 8086 2280 - SoC transaction router
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device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
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device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
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device pci 0b.0 on end # 8086 22dc - ?
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device pci 10.0 on end # 8086 2294 - MMC Port
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device pci 11.0 off end # 8086 0F15 - SDIO Port
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device pci 12.0 on end # 8086 0F16 - SD Port
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device pci 13.0 off end # 8086 22a3 - Sata controller
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device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time
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device pci 15.0 on end # 8086 22a8 - LP Engine Audio
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device pci 16.0 off end # 8086 22b7 - USB device
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device pci 18.0 on end # 8086 22c0 - SIO - DMA
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device pci 18.1 off end # 8086 22c1 - I2C Port 1
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device pci 18.2 on end # 8086 22c2 - I2C Port 2
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device pci 18.3 off end # 8086 22c3 - I2C Port 3
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device pci 18.4 off end # 8086 22c4 - I2C Port 4
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device pci 18.5 on end # 8086 22c5 - I2C Port 5
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device pci 18.6 on end # 8086 22c6 - I2C Port 6
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device pci 18.7 off end # 8086 22c7 - I2C Port 7
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device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine
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device pci 1b.0 on end # 8086 0F04 - HD Audio
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device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1
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device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2
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device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3
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device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4
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device pci 1e.0 on end # 8086 2286 - SIO - DMA
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device pci 1e.1 off end # 8086 0F08 - PWM 1
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device pci 1e.2 off end # 8086 0F09 - PWM 2
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device pci 1e.3 on end # 8086 228a - HSUART 1
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device pci 1e.4 off end # 8086 228c - HSUART 2
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device pci 1e.5 on end # 8086 228e - SPI 1
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device pci 1e.6 off end # 8086 2290 - SPI 2
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Bridge
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device pci 1f.3 off end # 8086 0F12 - SMBus 0
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end
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end
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@ -0,0 +1,259 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <mainboard/google/cyan/irqroute.h>
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#include <soc/gpio.h>
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#include <stdlib.h>
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/* South East Community */
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static const struct soc_gpio_map gpse_gpio_map[] = {
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Native_M1,/* MF_PLT_CLK0 */
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GPIO_NC, /* 01 PWM1 */
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GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
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GPIO_NC, /* 03 MF_PLT_CLK4 */
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GPIO_NC, /* 04 MF_PLT_CLK3 */
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GPIO_NC, /* PWM0 05 */
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GPIO_NC, /* 06 MF_PLT_CLK5 */
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GPIO_NC, /* 07 MF_PLT_CLK2 */
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GPIO_NC, /* 15 SDMMC2_D3_CD_B */
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Native_M1, /* 16 SDMMC1_CLK */
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NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
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GPIO_NC, /* 18 SDMMC2_D1 */
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GPIO_NC, /* 19 SDMMC2_CLK */
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NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
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GPIO_NC, /* 21 SDMMC2_D2 */
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GPIO_NC, /* 22 SDMMC2_CMD */
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NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
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NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
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GPIO_NC, /* 25 SDMMC2_D0 */
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NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
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GPIO_NC, /* 30 SDMMC3_D1 */
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GPIO_NC, /* 31 SDMMC3_CLK */
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GPIO_NC, /* 32 SDMMC3_D3 */
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GPIO_NC, /* 33 SDMMC3_D2 */
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GPIO_NC, /* 34 SDMMC3_CMD */
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GPIO_NC, /* 35 SDMMC3_D0 */
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NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
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NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */
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NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
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Native_M1, /* 48 LPC_FRAMEB */
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Native_M1, /* 49 MF_LPC_CLKOUT1 */
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NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
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Native_M1, /* 51 MF_LPC_CLKOUT0 */
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NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
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Native_M1,/* SPI1_MISO */
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Native_M1, /* 61 SPI1_CS0_B */
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Native_M1, /* SPI1_CLK */
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NATIVE_PU20K(1), /* 63 MMC1_D6 */
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Native_M1, /* 62 SPI1_MOSI */
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NATIVE_PU20K(1), /* 65 MMC1_D5 */
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GPIO_NC, /* SPI1_CS1_B 66 */
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NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
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NATIVE_PU20K(1), /* 68 MMC1_D7 */
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GPIO_NC, /* 69 MMC1_RCLK */
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Native_M1, /* 75 GPO USB_OC1_B */
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Native_M1, /* 76 PMU_RESETBUTTON_B */
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GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
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/* GPIO_ALERT 77 */
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GPIO_NC, /* 78 SDMMC3_PWR_EN_B */
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GPIO_NC, /* 79 GPI ILB_SERIRQ */
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Native_M1, /* 80 USB_OC0_B */
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NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */
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GPIO_NC, /* 82 spkr asummed gpio number */
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Native_M1, /* 83 SUSPWRDNACK */
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SPARE_PIN,/* 84 spare pin */
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GPIO_NC, /* 85 SDMMC3_1P8_EN */
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GPIO_END
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};
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/* South West Community */
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static const struct soc_gpio_map gpsw_gpio_map[] = {
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GPIO_NC, /* 00 FST_SPI_D2 */
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Native_M1, /* 01 FST_SPI_D0 */
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Native_M1, /* 02 FST_SPI_CLK */
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GPIO_NC, /* 03 FST_SPI_D3 */
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GPIO_NC, /* GPO FST_SPI_CS1_B */
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Native_M1, /* 05 FST_SPI_D1 */
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Native_M1, /* 06 FST_SPI_CS0_B */
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GPIO_NC, /* 07 FST_SPI_CS2_B */
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GPIO_NC, /* 15 UART1_RTS_B */
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Native_M2, /* 16 UART1_RXD */
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GPIO_NC, /* 17 UART2_RXD */
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GPIO_NC, /* 18 UART1_CTS_B */
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GPIO_NC, /* 19 UART2_RTS_B */
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Native_M2, /* 20 UART1_TXD */
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GPIO_NC, /* 21 UART2_TXD */
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GPIO_NC, /* 22 UART2_CTS_B */
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GPIO_NC, /* 30 MF_HDA_CLK */
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GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
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GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
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GPIO_NC, /* 33 MF_HDA_SDO */
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GPIO_NC, /* 34 MF_HDA_DOCKRSTB */
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GPIO_NC, /* 35 MF_HDA_SYNC */
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GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
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GPIO_NC, /* 37 MF_HDA_DOCKENB */
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NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
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GPIO_NC, /* 47 I2C6_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
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GPIO_NC, /* 49 I2C_NFC_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */
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GPIO_NC, /* 51 I2C6_SCL */
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GPIO_NC, /* 52 I2C_NFC_SCL */
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NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
|
||||
GPIO_NC, /* 61 I2C0_SDA */
|
||||
GPIO_NC, /* 62 I2C2_SDA */
|
||||
NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
|
||||
GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
|
||||
GPIO_NC, /* 65 I2C0_SCL */
|
||||
GPIO_NC, /* 66 I2C2_SCL */
|
||||
GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
|
||||
GPIO_OUT_HIGH, /* 75 SATA_GP0 */
|
||||
GPIO_NC,
|
||||
/* 76 GPI SATA_GP1 */
|
||||
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
|
||||
GPIO_NC, /* 80 SATA_GP3 */
|
||||
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
|
||||
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
|
||||
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
|
||||
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
|
||||
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
|
||||
Native_M1, /* 90 PCIE_CLKREQ0B */
|
||||
GPIO_NC, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
|
||||
Native_M1, /* 92 GP_SSP_2_CLK */
|
||||
NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
|
||||
Native_M1, /* 94 GP_SSP_2_RXD */
|
||||
GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
|
||||
/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
|
||||
Native_M1, /* 96 GP_SSP_2_FS */
|
||||
NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
|
||||
/* North Community */
|
||||
static const struct soc_gpio_map gpn_gpio_map[] = {
|
||||
GPIO_NC, /* 00 GPIO_DFX0 */
|
||||
GPIO_NC, /* 01 GPIO_DFX3 */
|
||||
GPIO_NC, /* 02 GPIO_DFX7 */
|
||||
GPIO_NC, /* 03 GPIO_DFX1 */
|
||||
GPIO_NC, /* 04 GPIO_DFX5 */
|
||||
GPIO_NC, /* 05 GPIO_DFX4 */
|
||||
GPIO_NC, /* 06 GPIO_DFX8 */
|
||||
GPIO_NC, /* 07 GPIO_DFX2 */
|
||||
GPIO_NC, /* 08 GPIO_DFX6 */
|
||||
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
|
||||
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
|
||||
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
|
||||
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
|
||||
/* 17 GPIO_SUS3 */
|
||||
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
|
||||
/* 18 GPIO_SUS7 */
|
||||
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
|
||||
/* 19 GPIO_SUS1 */
|
||||
GPIO_NC, /* 20 GPIO_SUS5 */
|
||||
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
|
||||
GPIO_NC, /* 22 GPIO_SUS4 */
|
||||
GPIO_NC,
|
||||
/* 23 SEC_GPIO_SUS8 */
|
||||
Native_M6, /* 24 GPIO_SUS2 */
|
||||
GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
|
||||
Native_M1, /* 26 CX_PREQ_B */
|
||||
GPIO_NC, /* 27 SEC_GPIO_SUS9 */
|
||||
Native_M1, /* 30 TRST_B */
|
||||
Native_M1, /* 31 TCK */
|
||||
GPIO_SKIP, /* 32 PROCHOT_B */
|
||||
GPIO_SKIP, /* 33 SVID0_DATA */
|
||||
Native_M1, /* 34 TMS */
|
||||
GPIO_NC, /* 35 CX_PRDY_B_2 */
|
||||
GPIO_NC, /* 36 TDO_2 */
|
||||
Native_M1, /* 37 CX_PRDY_B */
|
||||
GPIO_SKIP, /* 38 SVID0_ALERT_B */
|
||||
Native_M1, /* 39 TDO */
|
||||
GPIO_SKIP, /* 40 SVID0_CLK */
|
||||
Native_M1, /* 41 TDI */
|
||||
Native_M2, /* 45 GP_CAMERASB05 */
|
||||
Native_M2, /* 46 GP_CAMERASB02 */
|
||||
Native_M2, /* 47 GP_CAMERASB08 */
|
||||
Native_M2, /* 48 GP_CAMERASB00 */
|
||||
Native_M2, /* 49 GP_CAMERASBO6 */
|
||||
GPIO_NC, /* 50 GP_CAMERASB10 */
|
||||
Native_M2, /* 51 GP_CAMERASB03 */
|
||||
GPIO_NC, /* 52 GP_CAMERASB09 */
|
||||
Native_M2, /* 53 GP_CAMERASB01 */
|
||||
Native_M2, /* 54 GP_CAMERASB07 */
|
||||
GPIO_NC, /* 55 GP_CAMERASB11 */
|
||||
Native_M2, /* 56 GP_CAMERASB04 */
|
||||
GPIO_NC, /* 60 PANEL0_BKLTEN */
|
||||
Native_M1, /* 61 HV_DDI0_HPD */
|
||||
NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
|
||||
Native_M1, /* 63 PANEL1_BKLTCTL */
|
||||
NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
|
||||
GPIO_NC, /* 65 PANEL0_BKLTCTL */
|
||||
GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
|
||||
NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
|
||||
NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
|
||||
Native_M1, /* 69 PANEL1_VDDEN */
|
||||
Native_M1, /* 70 PANEL1_BKLTEN */
|
||||
GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
|
||||
GPIO_NC, /* 72 PANEL0_VDDEN */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
|
||||
/* East Community */
|
||||
static const struct soc_gpio_map gpe_gpio_map[] = {
|
||||
Native_M1, /* 00 PMU_SLP_S3_B */
|
||||
GPIO_NC, /* 01 PMU_BATLOW_B */
|
||||
Native_M1, /* 02 SUS_STAT_B */
|
||||
Native_M1, /* 03 PMU_SLP_S0IX_B */
|
||||
Native_M1, /* 04 PMU_AC_PRESENT */
|
||||
Native_M1, /* 05 PMU_PLTRST_B */
|
||||
Native_M1, /* 06 PMU_SUSCLK */
|
||||
GPIO_NC, /* 07 PMU_SLP_LAN_B */
|
||||
Native_M1, /* 08 PMU_PWRBTN_B */
|
||||
Native_M1, /* 09 PMU_SLP_S4_B */
|
||||
NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
|
||||
GPIO_NC, /* 11 PMU_WAKE_LAN_B */
|
||||
GPIO_NC, /* 15 MF_GPIO_3 */
|
||||
GPIO_NC, /* 16 MF_GPIO_7 */
|
||||
GPIO_NC, /* 17 MF_I2C1_SCL */
|
||||
GPIO_NC, /* 18 MF_GPIO_1 */
|
||||
GPIO_NC, /* 19 MF_GPIO_5 */
|
||||
GPIO_NC, /* 20 MF_GPIO_9 */
|
||||
GPIO_NC, /* 21 MF_GPIO_0 */
|
||||
GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
|
||||
GPIO_NC, /* 23 MF_GPIO_8 */
|
||||
GPIO_NC, /* 24 MF_GPIO_2 */
|
||||
GPIO_NC, /* 25 MF_GPIO_6 */
|
||||
GPIO_NC, /* 26 MF_I2C1_SDA */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
|
||||
static struct soc_gpio_config gpio_config = {
|
||||
/* BSW */
|
||||
.north = gpn_gpio_map,
|
||||
.southeast = gpse_gpio_map,
|
||||
.southwest = gpsw_gpio_map,
|
||||
.east = gpe_gpio_map
|
||||
};
|
||||
|
||||
struct soc_gpio_config *mainboard_get_gpios(void)
|
||||
{
|
||||
return &gpio_config;
|
||||
}
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2105 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
|
||||
#define DPTF_TSR0_PASSIVE 46
|
||||
#define DPTF_TSR0_CRITICAL 60
|
||||
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom"
|
||||
#define DPTF_TSR1_PASSIVE 48
|
||||
#define DPTF_TSR1_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "TMP432_Power_top"
|
||||
#define DPTF_TSR2_PASSIVE 68
|
||||
#define DPTF_TSR2_CRITICAL 80
|
||||
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
|
||||
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
/* Mainboard specific _PDL is 1GHz */
|
||||
Name (MPDL, 8)
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 500, 0, 0, 0, 0 },
|
||||
#ifdef DPTF_ENABLE_CHARGER
|
||||
/* Charger Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 1200, 0, 0, 0, 0 },
|
||||
#endif
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 550, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
2000, /* PowerLimitMinimum */
|
||||
5000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
8000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Matt DeVillier
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Elan trackpad */
|
||||
#include <acpi/trackpad_elan.asl>
|
||||
|
||||
/* Realtek audio codec */
|
||||
#include <acpi/codec_realtek.asl>
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#include <mainboard/google/cyan/irqroute.h>
|
||||
|
||||
/*
|
||||
* Calculation of gpio based irq.
|
||||
* Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
|
||||
* Max direct irq (MAX_DIRECT_IRQ) is 114.
|
||||
* Size of gpio banks are
|
||||
* GPSW_SIZE = 98
|
||||
* GPNC_SIZE = 73
|
||||
* GPEC_SIZE = 27
|
||||
* GPSE_SIZE = 86
|
||||
*/
|
||||
|
||||
/* KBD: Gpio index in N bank */
|
||||
#define BOARD_I8042_GPIO_INDEX 17
|
||||
/* Audio: Gpio index in SW bank */
|
||||
#define JACK_DETECT_GPIO_INDEX 95
|
||||
/* SCI: Gpio index in N bank */
|
||||
#define BOARD_SCI_GPIO_INDEX 15
|
||||
/* Trackpad: Gpio index in N bank */
|
||||
#define BOARD_TRACKPAD_GPIO_INDEX 18
|
||||
|
||||
#define BOARD_TRACKPAD_NAME "trackpad"
|
||||
#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
|
||||
#define BOARD_TRACKPAD_I2C_BUS 5
|
||||
#define BOARD_TRACKPAD_I2C_ADDR 0x15
|
||||
|
||||
/* SD CARD gpio */
|
||||
#define SDCARD_CD 81
|
||||
|
||||
#define AUDIO_CODEC_HID "10EC5650"
|
||||
#define AUDIO_CODEC_CID "10EC5650"
|
||||
#define AUDIO_CODEC_DDN "RTEK Codec Controller "
|
||||
#define AUDIO_CODEC_I2C_ADDR 0x1A
|
||||
|
||||
#define DPTF_CPU_PASSIVE 88
|
||||
#define DPTF_CPU_CRITICAL 90
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/romstage.h>
|
||||
#include <chip.h>
|
||||
#include <mainboard/google/cyan/spd/spd_util.h>
|
||||
|
||||
void mainboard_memory_init_params(struct romstage_params *params,
|
||||
MEMORY_INIT_UPD *memory_params)
|
||||
{
|
||||
int ram_id = get_ramid();
|
||||
|
||||
/*
|
||||
* RAMID = 4 - 4GiB Micron MT52L256M32D1PF
|
||||
* RAMID = 12 - 2GiB Micron MT52L256M32D1PF
|
||||
*/
|
||||
if (ram_id == 4 || ram_id == 12) {
|
||||
|
||||
/*
|
||||
* For new micron part, it requires read/receive
|
||||
* enable training before sending cmds to get MR8.
|
||||
* To override dram geometry settings as below:
|
||||
*
|
||||
* PcdDramWidth = x32
|
||||
* PcdDramDensity = 8Gb
|
||||
* PcdDualRankDram = disable
|
||||
*/
|
||||
memory_params->PcdRxOdtLimitChannel0 = 1;
|
||||
memory_params->PcdRxOdtLimitChannel1 = 1;
|
||||
memory_params->PcdDisableAutoDetectDram = 1;
|
||||
memory_params->PcdDramWidth = 2;
|
||||
memory_params->PcdDramDensity = 3;
|
||||
memory_params->PcdDualRankDram = 0;
|
||||
}
|
||||
|
||||
/* Update SPD data */
|
||||
memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;
|
||||
memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
|
||||
memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
|
||||
memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
* Copyright (C) 2017 Matt DeVillier
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <mainboard/google/cyan/spd/spd_util.h>
|
||||
|
||||
/*
|
||||
* 0b0000 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCE
|
||||
* 0b0001 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF
|
||||
* 0b0011 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR
|
||||
* 0b0100 - 4GiB total - 2 x 2GiB Micron MT52L256M32D1PF
|
||||
*
|
||||
* 0b1000 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE
|
||||
* 0b1001 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF
|
||||
* 0b1011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR
|
||||
* 0b1100 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF
|
||||
*/
|
||||
|
||||
int get_variant_spd_index(int ram_id, int *dual)
|
||||
{
|
||||
int spd_index = ram_id & 0x07;
|
||||
|
||||
/* Determine if single or dual channel memory system */
|
||||
/* RAMID3 is deterministic for banon */
|
||||
*dual = ((ram_id > 3) & 0x1) ? 0 : 1;
|
||||
|
||||
/* Display the RAM type */
|
||||
printk(BIOS_DEBUG, dual ? "4GiB " : "2GiB ");
|
||||
switch (spd_index) {
|
||||
case 0:
|
||||
printk(BIOS_DEBUG, "Samsung K4E8E304EE-EGCE\n");
|
||||
break;
|
||||
case 1:
|
||||
printk(BIOS_DEBUG, "Samsung K4E8E324EB-EGCF\n");
|
||||
break;
|
||||
case 2:
|
||||
printk(BIOS_DEBUG, "Unknown future LPDDR3\n");
|
||||
break;
|
||||
case 3:
|
||||
printk(BIOS_DEBUG, "Hynix H9CCNNN8JTBLAR\n");
|
||||
break;
|
||||
case 4:
|
||||
printk(BIOS_DEBUG, "Micron MT52L256M32D1PF\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return spd_index;
|
||||
}
|
||||
Loading…
Reference in New Issue