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soc/intel/cannonlake: Add PM methods to power gate SD card controller

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When system enters S0ix, system fails to power gate SD card
controller.

This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.

TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.

Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Vaibhav Shankar 2017-11-16 17:46:48 -08:00 committed by Martin Roth
parent d18db73d49
commit 6fd5a79d47
1 changed files with 17 additions and 0 deletions
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17
src/soc/intel/cannonlake/acpi/scs.asl
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@ -40,5 +40,22 @@ Scope (\_SB.PCI0) {
{ {
Name (_ADR, 0x00140005) Name (_ADR, 0x00140005)
OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
Field (SDPC, WordAcc, NoLock, Preserve)
{
Offset(0xA2), /* Device Power Gate config */
, 2,
PGEN, 1 /* PGE - PG Enable */
}
Method (_PS0, 0, Serialized)
{
Store (0, PGEN) /* Disable PG */
}
Method (_PS3, 0, Serialized)
{
Store (1, PGEN) /* Enable PG */
}
} /* Device (SDXC) */ } /* Device (SDXC) */
} }