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skylake: clear write-1-to-clear fields in power regs 

Explicitly clear all write-1-to-clear fields in the
appropriate power state registers. That way stale
state isn't left around from boot to boot. The
MMIO PMC registers are always added such that the
resource can be accessed from reg_script. It doesn't
hurt to add the resource, and it's actually more
informative by attaching the actual resources
owned by the device.

BUG=chrome-os-partner:43625
BRANCH=None
TEST=Built and boot glados. Did global reset. Noticed bits
     set. Did normal reset and saw those same bits no longer set.

Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290339

Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11186
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-08-04 21:04:02 -05:00
parent 04a066661d
commit 6fd5bd20d3
1 changed files with 18 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/soc/intel/skylake/pmc.c
View File

@ -51,23 +51,25 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
REG_SCRIPT_END REG_SCRIPT_END
}; };
static const struct reg_script pmc_write1_to_clear_script[] = {
REG_PCI_OR32(GEN_PMCON_A, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
REG_SCRIPT_END
};
static void pch_pmc_add_mmio_resources(device_t dev) static void pch_pmc_add_mmio_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
const u32 default_decode_base = PCH_PCR_BASE_ADDRESS;
/* /* Memory-mmapped I/O registers. */
* Till PCI enumeration happens we need to allocate the PMC base
* statically. Above the PCR base.
*/
if (PCH_PWRM_BASE_ADDRESS < default_decode_base) {
res = new_resource(dev, PWRMBASE); res = new_resource(dev, PWRMBASE);
res->base = PCH_PWRM_BASE_ADDRESS; res->base = PCH_PWRM_BASE_ADDRESS;
/* 64KB PMC size */ res->size = PCH_PWRM_BASE_SIZE;
res->size = 0x10000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE; IORESOURCE_FIXED | IORESOURCE_RESERVE;
}
} }
static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
@ -248,6 +250,9 @@ static void pmc_init(struct device *dev)
config_deep_s3(config->deep_s3_enable); config_deep_s3(config->deep_s3_enable);
config_deep_s5(config->deep_s5_enable); config_deep_s5(config->deep_s5_enable);
config_deep_sx(config->deep_sx_config); config_deep_sx(config->deep_sx_config);
/* Clear registers that contain write-1-to-clear bits. */
reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
} }
static struct device_operations device_ops = { static struct device_operations device_ops = {