nb/intel/x4x/x4x.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I75723fe087ef16f74ca93f6faa4d3468d7958a5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Angel Pons
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2a8ceefb27
commit
6fd9adbecb
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@ -16,11 +16,11 @@
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/*
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* D1:F0 PEG
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*/
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#define PEG_CAP 0xa2
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#define SLOTCAP 0xb4
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#define PEGLC 0xec
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#define D1F0_VCCAP 0x104
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#define D1F0_VC0RCTL 0x114
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#define PEG_CAP 0xa2
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#define SLOTCAP 0xb4
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#define PEGLC 0xec
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#define D1F0_VCCAP 0x104
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#define D1F0_VC0RCTL 0x114
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/*
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* Graphics frequencies
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@ -40,21 +40,18 @@
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* MCHBAR
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*/
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#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR8_AND_OR(x, and, or) \
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(MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR16_AND_OR(x, and, or) \
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(MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
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#define MCHBAR32_AND_OR(x, and, or) \
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(MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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#define CHDECMISC 0x111
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#define STACKED_MEM (1 << 1)
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@ -92,49 +89,49 @@
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* DMIBAR
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*/
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#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
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#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
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#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
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#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
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#define DMIVC0RCTL 0x14
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#define DMIVC1RCTL 0x20
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#define DMIVC1RSTS 0x26
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#define DMIESD 0x44
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#define DMILE1D 0x50
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#define DMILE1A 0x58
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#define DMILE2D 0x60
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#define DMILE2A 0x68
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#define DMIVC0RCTL 0x14
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#define DMIVC1RCTL 0x20
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#define DMIVC1RSTS 0x26
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#define DMIESD 0x44
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#define DMILE1D 0x50
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#define DMILE1A 0x58
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#define DMILE2D 0x60
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#define DMILE2A 0x68
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/*
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* EPBAR
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*/
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#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
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#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
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#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
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#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
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#define EPESD 0x44
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#define EPLE1D 0x50
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#define EPLE1A 0x58
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#define EPLE2D 0x60
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#define EPESD 0x44
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#define EPLE1D 0x50
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#define EPLE1A 0x58
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#define EPLE2D 0x60
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#define NOP_CMD 0x2
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#define PRECHARGE_CMD 0x4
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#define MRS_CMD 0x6
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#define EMRS_CMD 0x8
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#define EMRS1_CMD (EMRS_CMD | 0x10)
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#define EMRS2_CMD (EMRS_CMD | 0x20)
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#define EMRS3_CMD (EMRS_CMD | 0x30)
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#define ZQCAL_CMD 0xa
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#define CBR_CMD 0xc
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#define NORMALOP_CMD 0xe
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#define NOP_CMD 0x2
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#define PRECHARGE_CMD 0x4
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#define MRS_CMD 0x6
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#define EMRS_CMD 0x8
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#define EMRS1_CMD (EMRS_CMD | 0x10)
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#define EMRS2_CMD (EMRS_CMD | 0x20)
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#define EMRS3_CMD (EMRS_CMD | 0x30)
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#define ZQCAL_CMD 0xa
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#define CBR_CMD 0xc
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#define NORMALOP_CMD 0xe
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#define TOTAL_CHANNELS 2
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#define TOTAL_DIMMS 4
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#define TOTAL_BYTELANES 8
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#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS)
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#define RAW_CARD_UNPOPULATED 0xff
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#define RAW_CARD_POPULATED 0
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#define TOTAL_CHANNELS 2
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#define TOTAL_DIMMS 4
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#define TOTAL_BYTELANES 8
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#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS)
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#define RAW_CARD_UNPOPULATED 0xff
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#define RAW_CARD_POPULATED 0
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#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED)
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#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED)
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@ -194,9 +191,9 @@
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#define DDR3_MAX_CAS 18
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enum fsb_clock {
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FSB_CLOCK_800MHz = 0,
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FSB_CLOCK_1066MHz = 1,
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FSB_CLOCK_1333MHz = 2,
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FSB_CLOCK_800MHz = 0,
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FSB_CLOCK_1066MHz = 1,
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FSB_CLOCK_1333MHz = 2,
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};
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enum mem_clock {
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@ -204,8 +201,8 @@ enum mem_clock {
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MEM_CLOCK_533MHz = 1,
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MEM_CLOCK_667MHz = 2,
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MEM_CLOCK_800MHz = 3,
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MEM_CLOCK_1066MHz = 4,
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MEM_CLOCK_1333MHz = 5,
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MEM_CLOCK_1066MHz = 4,
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MEM_CLOCK_1333MHz = 5,
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};
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enum ddr {
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@ -256,7 +253,7 @@ enum n_banks {
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struct timings {
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unsigned int CAS;
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unsigned int tclk;
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unsigned int tclk;
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enum fsb_clock fsb_clk;
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enum mem_clock mem_clk;
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unsigned int tRAS;
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@ -270,15 +267,14 @@ struct timings {
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};
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struct dimminfo {
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unsigned int card_type; /* 0xff: unpopulated,
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0xa - 0xf: raw card type A - F */
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unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */
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enum chip_width width;
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unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
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enum n_banks n_banks;
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unsigned int ranks;
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unsigned int rows;
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unsigned int cols;
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u16 spd_crc;
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u16 spd_crc;
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u8 mirrored;
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};
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@ -342,8 +338,7 @@ u32 ddr_to_mhz(u32 speed);
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u32 test_address(int channel, int rank);
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void dqsset(u8 ch, u8 lane, const struct dll_setting *setting);
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void dqset(u8 ch, u8 lane, const struct dll_setting *setting);
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void rt_set_dqs(u8 channel, u8 lane, u8 rank,
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struct rt_dqs_setting *dqs_setting);
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void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting);
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int do_write_training(struct sysinfo *s);
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int do_read_training(struct sysinfo *s);
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void search_write_leveling(struct sysinfo *s);
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