nb/intel/x4x/x4x.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I75723fe087ef16f74ca93f6faa4d3468d7958a5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -44,17 +44,14 @@
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR8_AND_OR(x, and, or) \
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(MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
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#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR16_AND_OR(x, and, or) \
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(MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
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#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
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#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
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#define MCHBAR32_AND_OR(x, and, or) \
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#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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(MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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#define CHDECMISC 0x111
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#define CHDECMISC 0x111
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#define STACKED_MEM (1 << 1)
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#define STACKED_MEM (1 << 1)
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@ -270,8 +267,7 @@ struct timings {
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};
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};
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struct dimminfo {
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struct dimminfo {
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unsigned int card_type; /* 0xff: unpopulated,
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unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */
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0xa - 0xf: raw card type A - F */
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enum chip_width width;
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enum chip_width width;
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unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
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unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
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enum n_banks n_banks;
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enum n_banks n_banks;
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@ -342,8 +338,7 @@ u32 ddr_to_mhz(u32 speed);
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u32 test_address(int channel, int rank);
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u32 test_address(int channel, int rank);
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void dqsset(u8 ch, u8 lane, const struct dll_setting *setting);
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void dqsset(u8 ch, u8 lane, const struct dll_setting *setting);
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void dqset(u8 ch, u8 lane, const struct dll_setting *setting);
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void dqset(u8 ch, u8 lane, const struct dll_setting *setting);
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void rt_set_dqs(u8 channel, u8 lane, u8 rank,
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void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting);
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struct rt_dqs_setting *dqs_setting);
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int do_write_training(struct sysinfo *s);
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int do_write_training(struct sysinfo *s);
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int do_read_training(struct sysinfo *s);
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int do_read_training(struct sysinfo *s);
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void search_write_leveling(struct sysinfo *s);
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void search_write_leveling(struct sysinfo *s);
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