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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2004-01-13 22:18:03 +00:00
parent 24aa3c8cf1
commit 6ff2ab9649
4 changed files with 318 additions and 0 deletions

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##
## CPU initialization
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
##
## PPC7XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc

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/* Copyright 2000 AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
/*
* The aim of this code is to bring the machine from power-on to the point
* where we can jump to the the main LinuxBIOS entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
* out of ROM, generally at 0xfff00100.
*
* Before we jump to harwaremain() we want to do the following:
*
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
* - set up IBATs for RAM and ROM
*
*/
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
#define BSP_IOMASK2 BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
isync
/*
* Disable dcache and MMU, so we're in a known state
*/
li r0, 0
sync
mtspr HID0, r0
sync
mtmsr r0
isync
/*
* Invalidate D & I BATS
*/
mtibatu 0, r0
mtibatu 1, r0
mtibatu 2, r0
mtibatu 3, r0
isync
mtdbatu 0, r0
mtdbatu 1, r0
mtdbatu 2, r0
mtdbatu 3, r0
isync
/*
* Clear segment registers (LinuxBIOS doesn't use these)
*/
mtsr 0, r0
isync
mtsr 1, r0
isync
mtsr 2, r0
isync
mtsr 3, r0
isync
mtsr 4, r0
isync
mtsr 5, r0
isync
mtsr 6, r0
isync
mtsr 7, r0
isync
mtsr 8, r0
isync
mtsr 9, r0
isync
mtsr 10, r0
isync
mtsr 11, r0
isync
mtsr 12, r0
isync
mtsr 13, r0
isync
mtsr 14, r0
isync
mtsr 15, r0
isync
/*
* Set up DBATs
*
* DBAT0 covers RAM (0 -> 0x0FFFFFFF) (256Mb)
* DBAT1 covers PCI memory and ROM (0xFD000000 -> 0xFFFFFFFF) (64Mb)
* DBAT2 covers PCI memory (0x80000000 -> 0x8FFFFFFF) (256Mb)
* DBAT3 is not used
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE | BAT_GUARDED
mtdbatu 0, r3
mtdbatl 0, r2
isync
lis r2, BSP_IOREGION2@h
ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 1, r3
mtdbatl 1, r2
isync
lis r2, BSP_IOREGION1@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 2, r3
mtdbatl 2, r2
isync
/*
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE
mtibatu 0, r3
mtibatl 0, r2
isync
lis r2, _ROMBASE@h
#if ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#endif
ori r2, r2, BAT_READ_ONLY
mtibatu 1, r3
mtibatl 1, r2
isync
/*
* Enable MMU
*/
mfmsr r2
ori r2, r2, MSR_DR | MSR_IR
mtmsr r2
isync
sync
/*
* Enable and invalidate the L1 icache
*/
mfspr r2, HID0
ori r2, r2, HID0_ICE | HID0_ICFI
isync
mtspr HID0, r2
/*
* Enable and invalidate the L1 dcache
*/
mfspr r2, HID0
ori r2, r2, HID0_DCE | HID0_DCFI
sync
mtspr HID0, r2
/*
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*/
lis r1, DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
bdnz 0b

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##
## Config file for the Total Impact briQ
##
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses UART0_IO_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
##
## Set PCI registers
##
default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004
##
## Set UART base address
##
default UART0_IO_BASE=0xef600300
##
## Early board initialization, called from ppc_main()
##
initobject init.c
driver pci_bridge.c
arch ppc end
if CONFIG_BRIQ_750FX
cpu ppc/ppc7xx end
end
if CONFIG_BRIQ_7400
cpu ppc/mpc74xx end
end
##
## Include the secondary Configuration files
##
southbridge winbond/w83c553 end
##
## Build the objects we have code for in this directory.
##
addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"

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/*
* Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Do very early board initialization:
*
* - Configure External Bus (EBC)
* - Setup Flash
* - Setup NVRTC
* - Setup Board Control and Status Registers (BCSR)
* - Enable UART0 for debugging
*/
#include <ppc_asm.tmpl>
#include <ppc.h>
#include <ppc4xx.h>
#include <arch/io.h>
#include <timer.h>
void
board_init(void)
{
/*
* Configure FLASH
*/
mtebc(pb0cr, 0xFC0DC000);
mtebc(pb0ap, 0x02000000);
/*
* Configure NVTRC/BCSR
*/
mtebc(pb4cr, 0xF4058000);
mtebc(pb4ap, 0x04050000);
/*
* Enable PCI
*/
outb(0x80, 0xF4000001);
/*
* Enable UART0
*/
outb(0x20, 0xF4000003);
/*
* Cycle LEDs to show something is happening...
*/
outb(0x07, 0xF4000009);
udelay(100000);
outb(0x0B, 0xF4000009);
udelay(100000);
outb(0x0D, 0xF4000009);
udelay(100000);
outb(0x0E, 0xF4000009);
}