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vendorcode/intel/skykabylake: Update CpuConfigFspData.h file 

The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.

BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.

Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Barnali Sarkar 2017-02-03 13:28:46 +05:30 committed by Martin Roth
parent 0254c2d99f
commit 6ff7e8f550
1 changed files with 2 additions and 2 deletions
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4
src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
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@ -62,9 +62,9 @@ typedef union {
UINT32 TxtEnable : 1; UINT32 TxtEnable : 1;
UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
UINT32 RsvdBits : 15; ///< Reserved for future use UINT32 RsvdBits : 15; ///< Reserved for future use
EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. UINT32 Reserved;
} Bits; } Bits;
UINT32 Uint32[3]; UINT32 Uint32[2];
} CPU_CONFIG_FSP_DATA; } CPU_CONFIG_FSP_DATA;
#pragma pack (pop) #pragma pack (pop)