soc/amd: rename program_gpios to gpio_configure_pads

Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.

This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/mainboard/amd/bilby/early_gpio.c

@@ -31,5 +31,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 
 void mainboard_program_early_gpios(void)
 {
-	program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
 }

src/mainboard/amd/bilby/emmc_gpio.c

@@ -23,5 +23,5 @@ static const struct soc_amd_gpio emmc_gpios[] = {
 /* Don't call this if the board uses the LPC bus. */
 void mainboard_program_emmc_gpios(void)
 {
-	program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios));
+	gpio_configure_pads(emmc_gpios, ARRAY_SIZE(emmc_gpios));
 }

src/mainboard/amd/bilby/gpio.c

@@ -23,5 +23,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 
 void mainboard_program_gpios(void)
 {
-	program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+	gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
 }

src/mainboard/amd/gardenia/bootblock/bootblock.c

@@ -10,5 +10,5 @@ void bootblock_mainboard_early_init(void)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 	gpios = early_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }

src/mainboard/amd/gardenia/mainboard.c

@@ -69,7 +69,7 @@ static void mainboard_init(void *chip_info)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 	gpios = gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 /*************************************************

src/mainboard/amd/majolica/early_gpio.c

@@ -14,5 +14,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 
 void mainboard_program_early_gpios(void)
 {
-	program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
 }

src/mainboard/amd/mandolin/emmc_gpio.c

@@ -23,5 +23,5 @@ static const struct soc_amd_gpio emmc_gpios[] = {
 /* Don't call this if the board uses the LPC bus. */
 void mainboard_program_emmc_gpios(void)
 {
-	program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios));
+	gpio_configure_pads(emmc_gpios, ARRAY_SIZE(emmc_gpios));
 }

src/mainboard/amd/mandolin/variants/cereme/early_gpio.c

@@ -28,5 +28,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 
 void mainboard_program_early_gpios(void)
 {
-	program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
 }

src/mainboard/amd/mandolin/variants/cereme/gpio.c

@@ -29,5 +29,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 
 void mainboard_program_gpios(void)
 {
-	program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+	gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
 }

src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c

@@ -32,5 +32,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
 
 void mainboard_program_early_gpios(void)
 {
-	program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
 }

src/mainboard/amd/mandolin/variants/mandolin/gpio.c

@@ -34,5 +34,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 
 void mainboard_program_gpios(void)
 {
-	program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+	gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
 }

src/mainboard/amd/padmelon/bootblock/bootblock.c

@@ -46,5 +46,5 @@ void bootblock_mainboard_init(void)
 	const struct soc_amd_gpio *gpios;
 
 	gpios = early_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }

src/mainboard/amd/padmelon/mainboard.c

@@ -98,7 +98,7 @@ static void mainboard_init(void *chip_info)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 	gpios = gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 /*************************************************

src/mainboard/google/guybrush/smihandler.c

@@ -22,7 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
 
 	gpios = variant_sleep_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 int mainboard_smi_apmc(u8 apmc)

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -362,7 +362,7 @@ __weak void variant_fpmcu_reset(void)
 		/* EN_PWR_FP */
 		PAD_GPO(GPIO_32, LOW),
 	};
-	program_gpios(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table));
+	gpio_configure_pads(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table));
 }
 
 __weak void variant_finalize_gpios(void)
@@ -380,6 +380,6 @@ __weak void variant_finalize_gpios(void)
 		/* Deassert the FPMCU reset to enable the FPMCU */
 		gpio_set(GPIO_11, 1); /* FPMCU_RST_L */
 	} else {
-		program_gpios(disable_fpmcu_table, ARRAY_SIZE(disable_fpmcu_table));
+		gpio_configure_pads(disable_fpmcu_table, ARRAY_SIZE(disable_fpmcu_table));
 	}
 }

src/mainboard/google/guybrush/verstage.c

@@ -13,7 +13,7 @@ static void setup_gpio(void)
 
 	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
 		gpios = variant_early_gpio_table(&num_gpios);
-		program_gpios(gpios, num_gpios);
+		gpio_configure_pads(gpios, num_gpios);
 	}
 }
 

src/mainboard/google/kahlee/bootblock/bootblock.c

@@ -17,10 +17,10 @@ void bootblock_mainboard_early_init(void)
 	mainboard_ec_init();
 
 	gpios = variant_wlan_rst_early_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 
 	gpios = variant_early_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 void bootblock_mainboard_init(void)

src/mainboard/google/kahlee/mainboard.c

@@ -115,7 +115,7 @@ static void mainboard_init(void *chip_info)
 	mainboard_ec_init();
 
 	gpios = variant_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 
 	/* Initialize i2c busses that were not initialized in bootblock */
 	i2c_soc_init();

src/mainboard/google/kahlee/romstage.c

@@ -21,7 +21,7 @@ void mainboard_romstage_entry(void)
 	const struct soc_amd_gpio *gpios;
 
 	gpios = variant_romstage_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 
 	variant_romstage_entry();
 }

src/mainboard/google/mancomb/bootblock.c

@@ -15,7 +15,7 @@ void bootblock_mainboard_early_init(void)
 
 	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
 		gpios = variant_early_gpio_table(&num_gpios);
-		program_gpios(gpios, num_gpios);
+		gpio_configure_pads(gpios, num_gpios);
 	}
 
 	printk(BIOS_DEBUG, "Bootblock configure eSPI\n");

src/mainboard/google/mancomb/smihandler.c

@@ -22,7 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
 
 	gpios = variant_sleep_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 int mainboard_smi_apmc(u8 apmc)

src/mainboard/google/mancomb/verstage.c

@@ -10,7 +10,7 @@ static void setup_gpio(void)
 	size_t num_gpios;
 	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
 		gpios = variant_early_gpio_table(&num_gpios);
-		program_gpios(gpios, num_gpios);
+		gpio_configure_pads(gpios, num_gpios);
 	}
 }
 

src/mainboard/google/zork/bootblock.c

@@ -10,7 +10,7 @@ void bootblock_mainboard_early_init(void)
 	const struct soc_amd_gpio *gpios;
 
 	gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type());
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 
 	variant_pcie_gpio_configure();
 }

src/mainboard/google/zork/smihandler.c

@@ -26,7 +26,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 					MAINBOARD_EC_S5_WAKE_EVENTS);
 
 	gpios = variant_sleep_gpio_table(&num_gpios, slp_typ);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 int mainboard_smi_apmc(u8 apmc)

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

@@ -183,7 +183,7 @@ static void wifi_power_reset_configure_active_low_power(void)
 		/* EN_PWR_WIFI_L */
 		PAD_GPO(GPIO_42, LOW),
 	};
-	program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
+	gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 
 	mdelay(50);
 	gpio_set(GPIO_29, 0);
@@ -208,7 +208,7 @@ static void wifi_power_reset_configure_active_high_power(void)
 		/* EN_PWR_WIFI */
 		PAD_GPO(GPIO_42, LOW),
 	};
-	program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
+	gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 
 	mdelay(10);
 	gpio_set(GPIO_42, 1);
@@ -242,7 +242,7 @@ static void wifi_power_reset_configure_pre_v3(void)
 		/* EN_PWR_WIFI */
 		PAD_GPO(GPIO_29, LOW),
 	};
-	program_gpios(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
+	gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
 
 	mdelay(10);
 	gpio_set(GPIO_29, 1);
@@ -267,7 +267,7 @@ __weak void variant_pcie_gpio_configure(void)
 		PAD_GPO(GPIO_142, HIGH),
 	};
 
-	program_gpios(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table));
+	gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table));
 
 	/* Deassert PCIE_RST1_L */
 	gpio_set(GPIO_27, 1);

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c

@@ -195,7 +195,7 @@ static void wifi_power_reset_configure_active_low_power(void)
 		/* EN_PWR_WIFI_L */
 		PAD_GPO(GPIO_42, LOW),
 	};
-	program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
+	gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 
 }
 
@@ -218,7 +218,7 @@ static void wifi_power_reset_configure_active_high_power(void)
 		/* EN_PWR_WIFI */
 		PAD_GPO(GPIO_42, LOW),
 	};
-	program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
+	gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 
 	mdelay(10);
 	gpio_set(GPIO_42, 1);
@@ -252,7 +252,7 @@ static void wifi_power_reset_configure_pre_v3(void)
 		/* EN_PWR_WIFI */
 		PAD_GPO(GPIO_29, LOW),
 	};
-	program_gpios(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
+	gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
 
 	mdelay(10);
 	gpio_set(GPIO_29, 1);
@@ -275,7 +275,7 @@ __weak void variant_pcie_gpio_configure(void)
 		PAD_GPO(GPIO_142, HIGH),
 	};
 
-	program_gpios(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table));
+	gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table));
 
 	if (variant_uses_v3_schematics())
 		wifi_power_reset_configure_v3();

src/mainboard/google/zork/verstage.c

@@ -11,7 +11,7 @@ static void setup_gpio(void)
 
 	printk(BIOS_DEBUG, "Setting GPIOs\n");
 	gpios = variant_early_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 	printk(BIOS_DEBUG, "GPIOs setup\n");
 }
 

src/mainboard/pcengines/apu2/romstage.c

@@ -60,14 +60,14 @@ const struct soc_amd_gpio gpio_apu5[] = {
 
 static void early_lpc_init(void)
 {
-	program_gpios(gpio_common, ARRAY_SIZE(gpio_common));
+	gpio_configure_pads(gpio_common, ARRAY_SIZE(gpio_common));
 
 	if (CONFIG(BOARD_PCENGINES_APU2))
-		program_gpios(gpio_apu2, ARRAY_SIZE(gpio_apu2));
+		gpio_configure_pads(gpio_apu2, ARRAY_SIZE(gpio_apu2));
 
 	if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4))
-		program_gpios(gpio_apu34, ARRAY_SIZE(gpio_apu34));
+		gpio_configure_pads(gpio_apu34, ARRAY_SIZE(gpio_apu34));
 
 	if (CONFIG(BOARD_PCENGINES_APU5))
-		program_gpios(gpio_apu5, ARRAY_SIZE(gpio_apu5));
+		gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5));
 }

src/soc/amd/cezanne/uart.c

@@ -45,7 +45,7 @@ void set_uart_config(unsigned int idx)
 	if (idx >= ARRAY_SIZE(uart_info))
 		return;
 
-	program_gpios(uart_info[idx].mux, 2);
+	gpio_configure_pads(uart_info[idx].mux, 2);
 }
 
 static const char *uart_acpi_name(const struct device *dev)

src/soc/amd/common/block/gpio_banks/gpio.c

@@ -309,7 +309,7 @@ void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg,
 	master_switch_set(GPIO_INTERRUPT_EN);
 }
 
-void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
+void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 {
 	gpio_configure_pads_with_override(gpio_list_ptr, size, NULL, 0);
 }

src/soc/amd/common/block/i2c/i2c.c

@@ -164,7 +164,7 @@ void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_
 		   that will be changed need to be saved first */
 		gpio_save_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]);
 		/* Program SCL GPIO as output driven high */
-		program_gpios(&reset_info->i2c_scl[i].pin, 1);
+		gpio_configure_pads(&reset_info->i2c_scl[i].pin, 1);
 	}
 
 	/*

src/soc/amd/common/block/include/amdblocks/gpio_banks.h

@@ -86,7 +86,7 @@ uintptr_t gpio_get_address(gpio_t gpio_num);
  *
  * @return none
  */
-void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size);
+void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size);
 /* Return the interrupt status and clear if set. */
 int gpio_interrupt_status(gpio_t gpio);
 /* Implemented by soc, provides table of available GPIO mapping to Gevents */

src/soc/amd/picasso/uart.c

@@ -53,7 +53,7 @@ void set_uart_config(unsigned int idx)
 	if (idx >= ARRAY_SIZE(uart_info))
 		return;
 
-	program_gpios(uart_info[idx].mux, 2);
+	gpio_configure_pads(uart_info[idx].mux, 2);
 }
 
 static const char *uart_acpi_name(const struct device *dev)