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mb/intel/adlrvp: Add support for DDR5 memory 

This patch adds DDR5 memory configuration parameters to FSP.

TEST=Able to build and boot ADLRVP with DDR5 memory.

Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-10-28 13:50:19 +05:30
parent 1410224cf4
commit 7029665482
3 changed files with 21 additions and 2 deletions
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5
src/mainboard/intel/adlrvp/romstage_fsp_params.c
View File

@ -36,7 +36,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
.spd_spec.spd_index = get_spd_index(),
};
const struct spd_info ddr4_spd_info = {
const struct spd_info ddr4_ddr5_spd_info = {
.read_type = READ_SMBUS,
.spd_spec = {
.spd_smbus_address = {
@ -51,7 +51,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
switch (board_id) {
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);
case ADL_P_DDR5:
memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated);
break;
case ADL_P_LP4_1:
case ADL_P_LP4_2:

16
src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
View File

@ -54,6 +54,20 @@ static const struct mb_cfg lpddr4_mem_config = {
.UserBd = BOARD_TYPE_MOBILE,
};
static const struct mb_cfg ddr5_mem_config = {
/* Baseboard uses only 100ohm Rcomp resistors */
.rcomp_resistor = {100, 100, 100},
/* Baseboard Rcomp target values */
.rcomp_targets = {50, 30, 30, 30, 27},
.dq_pins_interleaved = true,
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
};
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@ -62,6 +76,8 @@ const struct mb_cfg *variant_memory_params(void)
return &lpddr4_mem_config;
else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2)
return &ddr4_mem_config;
else if (board_id == ADL_P_DDR5)
return &ddr5_mem_config;
die("unsupported board id : 0x%x\n", board_id);
}

2
src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
View File

@ -12,6 +12,8 @@ enum adl_boardid {
/* ADL-P LPDDR4 RVPs */
ADL_P_LP4_1 = 0x10,
ADL_P_LP4_2 = 0x11,
/* ADL-P DDR5 RVPs */
ADL_P_DDR5 = 0x12,
/* ADL-P DDR4 RVPs */
ADL_P_DDR4_1 = 0x14,
ADL_P_DDR4_2 = 0x3F,