From 70299d916891b718606cad151cf56b1d410cf96a Mon Sep 17 00:00:00 2001
From: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Date: Tue, 16 Mar 2021 10:31:23 +0530
Subject: [PATCH] mb/google/brya: Enable display and DSP audio UPD

This patch includes changes to enable display and DSP audio UPD.

BUG=b:181219097,b:183482000
TEST=Audio sound card is detected and listed by the linux kernel.
Audio playback and capture is working on the Brya.

Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 4ef1da9bf9..6a15b9a240 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -71,6 +71,12 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
+	# HD Audio
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+	register "PchHdaIDispCodecEnable" = "1"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |