soc/amd/picasso: Enable eSPI capability for Picasso
This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. Additionally, it also calls espi_setup() and espi_configure_decodes() if mainboard enables use of eSPI and skips LPC decodes in that case. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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@ -12,6 +12,7 @@
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/espi.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/spi.h>
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@ -202,13 +203,20 @@ static void fch_smbus_init(void)
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asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
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}
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static void lpc_configure_decodes(void)
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{
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if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
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lpc_enable_port80();
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}
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/* Before console init */
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void fch_pre_init(void)
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{
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lpc_early_init();
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if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
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&& CONFIG(PICASSO_LPC_IOMUX))
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lpc_enable_port80();
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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lpc_configure_decodes();
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fch_spi_early_init();
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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@ -280,6 +288,11 @@ void fch_early_init(void)
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
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espi_setup();
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espi_configure_decodes();
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}
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}
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void sb_enable(struct device *dev)
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