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soc/amd/picasso: Enable eSPI capability for Picasso 

This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables
the capability for using eSPI on Picasso.

Additionally, it also calls espi_setup() and espi_configure_decodes()
if mainboard enables use of eSPI and skips LPC decodes in that case.

BUG=b:153675913,b:154445472

Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-05-09 18:30:51 -07:00 committed by Patrick Georgi
parent ed8ceabf3e
commit 702cf30e98
2 changed files with 17 additions and 3 deletions
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1
src/soc/amd/picasso/Kconfig
View File

@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC select UDELAY_TSC
select SOC_AMD_COMMON select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS

19
src/soc/amd/picasso/southbridge.c
View File

@ -12,6 +12,7 @@
#include <amdblocks/amd_pci_util.h> #include <amdblocks/amd_pci_util.h>
#include <amdblocks/reset.h> #include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h>
#include <amdblocks/lpc.h> #include <amdblocks/lpc.h>
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <amdblocks/spi.h> #include <amdblocks/spi.h>
@ -202,13 +203,20 @@ static void fch_smbus_init(void)
asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
} }
static void lpc_configure_decodes(void)
{
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
lpc_enable_port80();
}
/* Before console init */ /* Before console init */
void fch_pre_init(void) void fch_pre_init(void)
{ {
lpc_early_init(); lpc_early_init();
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
&& CONFIG(PICASSO_LPC_IOMUX)) if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_enable_port80(); lpc_configure_decodes();
fch_spi_early_init(); fch_spi_early_init();
enable_acpimmio_decode_pm04(); enable_acpimmio_decode_pm04();
fch_smbus_init(); fch_smbus_init();
@ -280,6 +288,11 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing(); lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
espi_setup();
espi_configure_decodes();
}
} }
void sb_enable(struct device *dev) void sb_enable(struct device *dev)