mb/system76/lemp9: gpio: convert gpio.h to a cleaner format
Convert gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. This was done with the following fancy vim regex replacement commands. (Neither sed, nor awk multiline matching syntax are friends with me...) Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before pasting each command, press enter and see how the format changes. g#^\t//#d %s/^\t\t/\t/ g/PAD_.*$\n\n[^/]/s/\n// g#// NC#d %s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g %s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */ %s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */# Finally some indents and multiline comments need to be fixed manually. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Michael Niewöhner
parent
aaea66aca8
commit
702e60ad8a
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@ -8,523 +8,246 @@
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#ifndef __ACPI__
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/* Name format: <pad name> / <net/pin name in schematics> */
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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// UART2
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// UART2_RXD
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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// UART2_TXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
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PAD_NC(GPP_C22, UP_20K),
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// NC
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PAD_NC(GPP_C23, UP_20K),
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};
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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// GPD
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// Power Management
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// NC
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/* ------- GPIO Group GPD ------- */
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PAD_NC(GPD0, NONE),
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// ACPRESENT / AC_PRESENT
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */
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PAD_NC(GPD2, UP_20K),
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// PWRBTN# / PWR_BTN#
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
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// SLP_S3# / SUSB#_PCH
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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// SLP_S4# / SUSC#_PCH
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */
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PAD_NC(GPD6, UP_20K),
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// GPIO
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// NC
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PAD_NC(GPD7, NONE),
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// Clock Signals
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// SUSCLK / SUS_CLK
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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// Power Management
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// NC
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */
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PAD_NC(GPD9, UP_20K),
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// NC
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PAD_NC(GPD10, UP_20K),
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// NC
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PAD_NC(GPD11, UP_20K),
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// GPP_A
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// LPC
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// RCIN# / SB_KBCRST#
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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// LAD0 / LPC_AD0
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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// LAD1 / LPC_AD1
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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// LAD2 / LPC_AD2
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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// LAD3 / LPC_AD3
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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// LFRAME# / LPC_FRAME#
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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// SERIRQ
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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// GSPI0
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// PIRQA# / TPM_PIRQ#
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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// LPC
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// CLKRUN# / PM_CLKRUN#
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// Note: R209 is populated despite being marked no-stuff in schematic
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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// CLKOUT_LPC0 / PCLK_KBC
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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// NC
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* RCIN# / SB_KBCRST# */
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LAD0 / LPC_AD0 */
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LAD1 / LPC_AD1 */
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LAD2 / LPC_AD2 */
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LAD3 / LPC_AD3 */
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LFRAME# / LPC_FRAME# */
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* SERIRQ */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PIRQA# / TPM_PIRQ# */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# / PM_CLKRUN#
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Note: R209 is populated despite being
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marked no-stuff in schematic
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*/
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* CLKOUT_LPC0 / PCLK_KBC */
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PAD_NC(GPP_A10, UP_20K),
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// GSPI1
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// INTP_OUT (Type-C VBUS_SENSE; unused in cb)
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PAD_NC(GPP_A11, UP_20K),
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// ISH_GP
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// NC
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PAD_NC(GPP_A11, UP_20K), /* INTP_OUT
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(Type-C VBUS_SENSE; unused in cb)
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*/
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PAD_NC(GPP_A12, UP_20K),
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// Power Management
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// SUSWARN# (unused due to missing DeepSx support)
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PAD_NC(GPP_A13, UP_20K),
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// LPC
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// NC
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PAD_NC(GPP_A13, UP_20K), /* SUSWARN#
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(unused due to missing DeepSx support)
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*/
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PAD_NC(GPP_A14, UP_20K),
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// Power Management
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// NC
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PAD_NC(GPP_A15, UP_20K),
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// SD
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// NC
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PAD_NC(GPP_A16, UP_20K),
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// LEDKB_DET# (unused in cb; all devices of that model have KB LED)
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PAD_NC(GPP_A17, NONE),
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// ISH_GP
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// NC
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PAD_NC(GPP_A17, NONE), /* LEDKB_DET#
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(unused in cb; all devices of that
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model have KB LED)
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*/
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PAD_NC(GPP_A18, UP_20K),
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// NC
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PAD_NC(GPP_A19, UP_20K),
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// GPP_A20 / TEST_R
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PAD_CFG_GPO(GPP_A20, 0, DEEP),
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// NC
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PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_A20 / TEST_R */
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PAD_NC(GPP_A21, UP_20K),
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// NC
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PAD_NC(GPP_A22, UP_20K),
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// NC
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PAD_NC(GPP_A23, UP_20K),
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// GPP_B
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// Power
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// NC
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/* ------- GPIO Group GPP_B ------- */
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PAD_NC(GPP_B0, UP_20K),
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// NC
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PAD_NC(GPP_B1, UP_20K),
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// Power Management
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// CNVI_WAKE# (UART_WAKE# in M.2 spec; unused)
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PAD_NC(GPP_B2, UP_20K),
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// CPU Misc
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// GPP_B3 (touchpad interrupt)
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PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),
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// NC
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PAD_NC(GPP_B2, UP_20K), /* CNVI_WAKE#
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(UART_WAKE# in M.2 spec; unused)
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*/
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PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),/* GPP_B3 (touchpad interrupt) */
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PAD_NC(GPP_B4, UP_20K),
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// Clock Signals
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// NC
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PAD_NC(GPP_B5, UP_20K),
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// NC
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PAD_NC(GPP_B6, UP_20K),
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// SRCCLKREQ2# / WLAN_CLKREQ#
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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// SRCCLKREQ3# / CARD_CLKREQ#
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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// SRCCLKREQ4# / SSD2_CLKREQ#
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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// SRCCLKREQ5# / SSD1_CLKREQ#
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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// Power Management
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// NC
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# / WLAN_CLKREQ# */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3# / CARD_CLKREQ# */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# / SSD2_CLKREQ# */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* SRCCLKREQ5# / SSD1_CLKREQ# */
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PAD_NC(GPP_B11, NONE),
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// SLP_S0#
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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// PLT_RST#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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// SPKR
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// SPKR / PCH_SPKR
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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// GSPI0
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// NC
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */
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PAD_NC(GPP_B15, UP_20K),
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// NC
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PAD_NC(GPP_B16, UP_20K),
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// NC
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PAD_NC(GPP_B17, NONE),
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// NC
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PAD_NC(GPP_B18, UP_20K),
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// GSPI1
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// NC
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PAD_NC(GPP_B19, UP_20K),
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// NC
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PAD_NC(GPP_B20, UP_20K),
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// NC
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PAD_NC(GPP_B21, UP_20K),
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// NC
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PAD_NC(GPP_B22, UP_20K),
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// SMBUS
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// NC
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PAD_NC(GPP_B23, UP_20K),
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// GPP_C
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// SMBUS
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// SMBCLK / SMB_CLK_DDR
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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// SMBDATA / SMB_DAT_DDR
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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// NC
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */
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PAD_NC(GPP_C2, UP_20K),
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// NC
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PAD_NC(GPP_C3, UP_20K),
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// NC
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PAD_NC(GPP_C4, UP_20K),
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// NC
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PAD_NC(GPP_C5, UP_20K),
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// NC
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PAD_NC(GPP_C6, UP_20K),
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// NC
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PAD_NC(GPP_C7, UP_20K),
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// UART0
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// NC
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PAD_NC(GPP_C8, UP_20K),
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// NC
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PAD_NC(GPP_C9, UP_20K),
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// NC
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PAD_NC(GPP_C10, UP_20K),
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// NC
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PAD_NC(GPP_C11, UP_20K),
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// UART1
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// NC
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PAD_NC(GPP_C12, UP_20K),
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// GPP_C13 / SSD1_PWR_DN#
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PAD_CFG_GPO(GPP_C13, 1, PLTRST),
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// NC
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PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPP_C13 / SSD1_PWR_DN# */
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PAD_NC(GPP_C14, UP_20K),
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// NC
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PAD_NC(GPP_C15, UP_20K),
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// I2C
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// I2C0_SDA / T_SDA
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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// I2C0_SCL / T_SCL
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL */
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PAD_NC(GPP_C18, UP_20K),
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// NC
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PAD_NC(GPP_C19, UP_20K),
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// UART2
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// UART2_RXD
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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// UART2_TXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
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PAD_NC(GPP_C22, UP_20K),
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// NC
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PAD_NC(GPP_C23, UP_20K),
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// GPP_D
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// SPI1
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// NC
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, UP_20K),
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// NC
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PAD_NC(GPP_D1, UP_20K),
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// NC
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PAD_NC(GPP_D2, UP_20K),
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// NC
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PAD_NC(GPP_D3, UP_20K),
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// IMGCLKOUT
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// NC
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PAD_NC(GPP_D4, UP_20K),
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// I2C
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// NC
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PAD_NC(GPP_D5, UP_20K),
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// NC
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PAD_NC(GPP_D6, UP_20K),
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// NC
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PAD_NC(GPP_D7, UP_20K),
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// SB_BLON
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PAD_CFG_GPO(GPP_D8, 1, DEEP),
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// GSPI2
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// EC SWI#
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PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL),
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// DDR_TYPE_D10 (unused; there is only one on-board ram type/model)
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PAD_NC(GPP_D10, NONE),
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// BOARD_ID (unused in cb; we already know the device model)
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PAD_NC(GPP_D11, NONE),
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// NC
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PAD_CFG_GPO(GPP_D8, 1, DEEP), /* SB_BLON */
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PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), /* EC SWI# */
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PAD_NC(GPP_D10, NONE), /* DDR_TYPE_D10
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(unused; there is only one on-board
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ram type/model)
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*/
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PAD_NC(GPP_D11, NONE), /* BOARD_ID
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(unused in cb; we already know the
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device model)
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*/
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PAD_NC(GPP_D12, UP_20K),
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// UART0
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// NC
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PAD_NC(GPP_D13, UP_20K),
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// SSD2_PWR_DN#
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PAD_CFG_GPO(GPP_D14, 1, PLTRST),
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// NC
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PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* SSD2_PWR_DN# */
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PAD_NC(GPP_D15, UP_20K),
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// NC
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PAD_NC(GPP_D16, UP_20K),
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// DMIC
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// NC
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PAD_NC(GPP_D17, UP_20K),
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// NC
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PAD_NC(GPP_D18, UP_20K),
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// NC
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PAD_NC(GPP_D19, UP_20K),
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// NC
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PAD_NC(GPP_D20, UP_20K),
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// SPI1
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// TPM_DET# (currently unused in cb; there seem to be no devices without TPM)
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PAD_NC(GPP_D21, NONE),
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// DDR_TYPE_D22 (unused in cb; there is only one on-board ram type)
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PAD_NC(GPP_D22, NONE),
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// I2S
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// NC
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PAD_NC(GPP_D21, NONE), /* TPM_DET#
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(currently unused in cb; there seem
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to be no devices without TPM)
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*/
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PAD_NC(GPP_D22, NONE), /* DDR_TYPE_D22
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(unused in cb; there is only one
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on-board ram type)
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*/
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PAD_NC(GPP_D23, UP_20K),
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// GPP_E
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// SATA
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// NC
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/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, UP_20K),
|
||||
// SATAXPCIE1 / SATAGP1
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
// SATAXPCIE2 / SATAGP2
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
|
||||
// CPU Misc
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 */
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 / SATAGP2 */
|
||||
PAD_NC(GPP_E3, UP_20K),
|
||||
|
||||
// DEVSLP
|
||||
// NC
|
||||
PAD_NC(GPP_E4, UP_20K),
|
||||
// DEVSLP1
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
// DEVSLP2
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
|
||||
// CPU Misc
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* DEVSLP2 */
|
||||
PAD_NC(GPP_E7, UP_20K),
|
||||
|
||||
// SATA
|
||||
// NC
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
|
||||
// USB2
|
||||
// NC
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
|
||||
// Display Signals
|
||||
// DDPB_HPD0 / MUX_HPD
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
// DDPC_HPD1 / HDMI_HPD
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
// EC SMI#
|
||||
PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
|
||||
// EC SCI#
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
|
||||
// EDP_HPD
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPB_HPD0 / MUX_HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPC_HPD1 / HDMI_HPD */
|
||||
PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), /* EC SCI# */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
|
||||
PAD_NC(GPP_E18, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
// DPPC_CTRLCLK / HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
// DPPC_CTRLDATA / HDMI_CTRLDATA
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DPPC_CTRLCLK / HDMI_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DPPC_CTRLDATA / HDMI_CTRLDATA */
|
||||
PAD_NC(GPP_E22, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_E23, UP_20K),
|
||||
|
||||
// GPP_F
|
||||
// CNVI
|
||||
// NC
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_NC(GPP_F0, UP_20K),
|
||||
|
||||
// GPIO
|
||||
// NC
|
||||
PAD_NC(GPP_F1, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F2, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F3, UP_20K),
|
||||
|
||||
// CNVI
|
||||
// CNV_BRI_DT / CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
// CNV_BRI_RSP / CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
// CNV_RGI_DT / CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
// CNV_RGI_RSP / CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */
|
||||
PAD_NC(GPP_F8, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F9, UP_20K),
|
||||
|
||||
// GPIO
|
||||
// NC
|
||||
PAD_NC(GPP_F10, UP_20K),
|
||||
|
||||
// EMMC
|
||||
// NC
|
||||
PAD_NC(GPP_F11, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F12, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F13, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F14, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F15, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F16, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F17, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F18, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F19, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F20, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F21, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_F22, UP_20K),
|
||||
|
||||
// A4WP
|
||||
// NC
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
// GPP_G
|
||||
// SD
|
||||
// NC
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_NC(GPP_G0, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G1, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G2, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G3, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G4, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G5, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G6, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_G7, UP_20K),
|
||||
|
||||
// GPP_H
|
||||
// CNVI
|
||||
// NC
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, UP_20K),
|
||||
// CNV_RF_RESET# / CNVI_RST#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
// MODEM_CLKREQ / CNVI_CLKREQ
|
||||
PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3),
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# / CNVI_RST# */
|
||||
PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), /* MODEM_CLKREQ / CNVI_CLKREQ */
|
||||
PAD_NC(GPP_H3, UP_20K),
|
||||
|
||||
// I2C
|
||||
// I2C2_SDA / SMD_7411
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
// I2C2_SCL / SMC_7411
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C2_SDA / SMD_7411 */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C2_SCL / SMC_7411 */
|
||||
PAD_NC(GPP_H6, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H7, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H8, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H9, UP_20K),
|
||||
|
||||
// I2C
|
||||
// NC
|
||||
PAD_NC(GPP_H10, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H11, UP_20K),
|
||||
|
||||
// PCIE
|
||||
// NC
|
||||
PAD_NC(GPP_H12, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H13, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H14, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H15, UP_20K),
|
||||
|
||||
// Display Signals
|
||||
// NC
|
||||
PAD_NC(GPP_H16, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H17, UP_20K),
|
||||
|
||||
// CPU Power
|
||||
// CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
|
||||
// TIMESYNC
|
||||
// NC
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */
|
||||
PAD_NC(GPP_H19, UP_20K),
|
||||
|
||||
// IMGCLKOUT
|
||||
// NC
|
||||
PAD_NC(GPP_H20, UP_20K),
|
||||
|
||||
// GPIO
|
||||
// NC
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
// NC
|
||||
PAD_NC(GPP_H22, UP_20K),
|
||||
// NC
|
||||
PAD_NC(GPP_H23, UP_20K),
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue