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mb/google/taeko: Update the FIVR configurations 

This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.

BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kevin Chang 2021-11-04 19:35:31 +08:00 committed by Patrick Georgi
parent d74f6f5a5d
commit 70701eba8d
1 changed files with 13 additions and 0 deletions
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13
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -41,6 +41,19 @@ fw_config
end end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1250,
}"
register "TcssAuxOri" = "1" register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"