GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA: Rename assembly from .inc to .S 

Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-09-02 16:20:15 +03:00
parent 5fb2d3074f
commit 7076aa5745
3 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/agesa/Makefile.inc
View File

@ -24,7 +24,7 @@ ramstage-y += s3_mtrr.c
ifeq ($(CONFIG_AGESA_LEGACY), y) ifeq ($(CONFIG_AGESA_LEGACY), y)
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
else else
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
romstage-y += romstage.c romstage-y += romstage.c
endif endif

11
src/cpu/amd/agesa/cache_as_ram.inc → src/cpu/amd/agesa/cache_as_ram.S
View File

@ -16,20 +16,21 @@
/****************************************************************************** /******************************************************************************
* AMD Generic Encapsulated Software Architecture * AMD Generic Encapsulated Software Architecture
* *
* $Workfile:: cache_as_ram.inc * $Workfile:: cache_as_ram.S
* *
* Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier
* *
****************************************************************************** ******************************************************************************
*/ */
#include "gcccar.inc" #include "gcccar.inc"
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
.code32 .code32
.globl cache_as_ram_setup, cache_as_ram_setup_out .globl _cache_as_ram_setup, _cache_as_ram_setup_end
cache_as_ram_setup: _cache_as_ram_setup:
/* Preserve BIST. */ /* Preserve BIST. */
movd %eax, %mm0 movd %eax, %mm0
@ -130,4 +131,4 @@ disable_cache_as_ram:
stop: stop:
jmp stop jmp stop
cache_as_ram_setup_out: _cache_as_ram_setup_end:

2
src/cpu/amd/pi/Makefile.inc
View File

@ -17,7 +17,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
romstage-y += romstage.c romstage-y += romstage.c