White space and comment fixes for cache_as_ram.inc files so it's easier to spot
differences. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
35ed0e7ea3
commit
707fad0508
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@ -31,7 +31,7 @@
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#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
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#define CPUID_MASK 0x0ff00f00
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#define CPUID_MASK 0x0ff00f00
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#define CPUID_VAL_FAM10_ROTATED 0x0f000010
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#include <cpu/x86/mtrr.h>
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@ -127,13 +127,13 @@ CAR_FAM10_out:
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/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
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/* read-address has to be stored in the ecx register */
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movl $MSR_FAM10, %ecx
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movl $MSR_FAM10, %ecx
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/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
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rdmsr
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/* Set bit 35 to 1 in EAX */
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bts $35, %eax
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bts $35, %eax
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/* write back the modified register EDX:EAX to the MSR specified in ECX */
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wrmsr
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@ -157,13 +157,13 @@ enable_fixed_mtrr_dram_modify:
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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@ -231,15 +231,15 @@ clear_fixed_var_mtrr_out:
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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simplemask CacheSize, 0x8000
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wrmsr
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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simplemask CacheSize, 0
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wrmsr
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@ -253,7 +253,7 @@ clear_fixed_var_mtrr_out:
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#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
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/* disable cache */
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movl %cr0, %eax
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orl $(1 << 30),%eax
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orl $(0x1 << 30), %eax
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movl %eax, %cr0
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#endif
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@ -287,7 +287,7 @@ wbcache_post_fam10_setup:
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/* Enable the MTRRs and IORRs in SYSCFG */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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#endif
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@ -312,16 +312,17 @@ fam10_end_part1:
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outb %al, $0x80
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#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
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/* Read the range with lodsl*/
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/* Read the range with lodsl*/
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cld
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movl $CacheBase, %esi
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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rep stosl
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#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
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@ -395,7 +396,7 @@ CAR_FAM10_ap_out:
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call cache_as_ram_main
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/* We will not go back */
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movb $0xAF, %al /* Should never see this postcode */
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movb $0xAF, %al /* Should never see this postcode */
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outb %al, $0x80
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fixed_mtrr_msr:
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@ -1,6 +1,6 @@
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/*
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/*
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Tyan
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@ -10,153 +10,154 @@
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* Copyright (C) 2007,2008 Carl-Daniel Hailfinger
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* Copyright (C) 2008 VIA Technologies, Inc.
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* (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase CONFIG_DCACHE_RAM_BASE
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase CONFIG_DCACHE_RAM_BASE
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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movl %eax, %ebp
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CacheAsRam:
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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movl %eax,%cr0
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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movl %eax,%cr0
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invd
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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movl $0x00000c00, %eax
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wrmsr
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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movl %eax, %ecx
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xorl %eax, %eax
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* MTRRPhysBase */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x201, %ecx
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movl $0x201, %ecx
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/* This assumes we never access addresses above 2^36 in CAR. */
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movl $0x0000000f,%edx
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movl $(~(CacheSize-1)|0x800),%eax
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movl $0x0000000f,%edx
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movl $(~(CacheSize-1)|0x800),%eax
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wrmsr
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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/* MTRRPhysBase */
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x203, %ecx
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movl $0x0000000f,%edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000800, %eax
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movl $0x00000800, %eax
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wrmsr
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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cld
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize>>2), %ecx
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rep lodsl
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize>>2), %ecx
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rep lodsl
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize>>2), %ecx
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize >> 2), %ecx
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/* 0x5c5c5c5c is a memory test pattern.
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* TODO: Check if everything works with the zero pattern as well. */
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/*xorl %eax, %eax*/
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xorl $0x5c5c5c5c,%eax
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rep stosl
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* TODO: Check if everything works with the zero pattern as well. */
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/*xorl %eax, %eax*/
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xorl $0x5c5c5c5c,%eax
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rep stosl
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movl CONFIG_XIP_ROM_BASE, %esi
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movl %esi, %edi
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movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
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rep lodsl
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movl CONFIG_XIP_ROM_BASE, %esi
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movl %esi, %edi
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movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
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rep lodsl
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/* The key point of this CAR code is C7 cache does not turn into
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* "no fill" mode, which is not compatible with general CAR code.
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*/
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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#ifdef CARTEST
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testok: movb $0x40,%al
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outb %al, $0x80
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xorl %edx, %edx
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xorl %eax, %eax
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movl $0x5c5c,%edx
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xorl %edx, %edx
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xorl %eax, %eax
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movl $0x5c5c,%edx
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pushl %edx
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pushl %edx
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pushl %edx
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pushl %edx
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pushl %edx
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popl %esi
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popl %esi
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popl %eax
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popl %eax
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popl %eax
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popl %esi
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popl %esi
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popl %eax
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popl %eax
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popl %eax
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cmpl %edx,%eax
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jne stackerr
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#endif
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call amd64_main
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pushl %eax /* bist */
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call amd64_main
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/* We will not go back */
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fixed_mtrr_msr:
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|
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|
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@ -1,6 +1,6 @@
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/*
|
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
|
||||
* Copyright (C) 2005 Eswar Nallusamy, LANL
|
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* Copyright (C) 2005 Tyan
|
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|
|
@ -8,16 +8,16 @@
|
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* Copyright (C) 2007 coresystems GmbH
|
||||
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
||||
* Copyright (C) 2007 Carl-Daniel Hailfinger
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
|
@ -28,107 +28,107 @@
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/* other's is the same as AMD except remove amd specific msr */
|
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
|
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#define CacheBase (0xd0000 - CacheSize)
|
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#define CacheBase (0xd0000 - CacheSize)
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|
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
|
||||
movl %eax, %ebp
|
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movl %eax, %ebp
|
||||
|
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CacheAsRam:
|
||||
/* hope we can skip the double set for normal part */
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
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|
||||
// Check whether the processor has HT capability
|
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movl $01, %eax
|
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cpuid
|
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btl $28, %edx
|
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jnc NotHtProcessor
|
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bswapl %ebx
|
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cmpb $01, %bh
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jbe NotHtProcessor
|
||||
// Check whether the processor has HT capability
|
||||
movl $01, %eax
|
||||
cpuid
|
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btl $28, %edx
|
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jnc NotHtProcessor
|
||||
bswapl %ebx
|
||||
cmpb $01, %bh
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jbe NotHtProcessor
|
||||
|
||||
// It is a HT processor; Send SIPI to the other logical processor
|
||||
// within this processor so that the CAR related common system registers
|
||||
// are programmed accordingly
|
||||
// It is a HT processor; Send SIPI to the other logical processor
|
||||
// within this processor so that the CAR related common system registers
|
||||
// are programmed accordingly
|
||||
|
||||
// Use some register that is common to both logical processors
|
||||
// as semaphore. Refer Appendix B, Vol.3
|
||||
xorl %eax, %eax
|
||||
xorl %edx, %edx
|
||||
movl $0x250, %ecx
|
||||
wrmsr
|
||||
// Use some register that is common to both logical processors
|
||||
// as semaphore. Refer Appendix B, Vol.3
|
||||
xorl %eax, %eax
|
||||
xorl %edx, %edx
|
||||
movl $0x250, %ecx
|
||||
wrmsr
|
||||
|
||||
// Figure out the logical AP's APIC ID; the following logic will work
|
||||
// only for processors with 2 threads
|
||||
// Refer to Vol 3. Table 7-1 for details about this logic
|
||||
movl $0xFEE00020, %esi
|
||||
movl (%esi), %ebx
|
||||
andl $0xFF000000, %ebx
|
||||
bswapl %ebx
|
||||
btl $0, %ebx
|
||||
jnc LogicalAP0
|
||||
andb $0xFE, %bl
|
||||
jmp Send_SIPI
|
||||
// Figure out the logical AP's APIC ID; the following logic will work
|
||||
// only for processors with 2 threads
|
||||
// Refer to Vol 3. Table 7-1 for details about this logic
|
||||
movl $0xFEE00020, %esi
|
||||
movl (%esi), %ebx
|
||||
andl $0xFF000000, %ebx
|
||||
bswapl %ebx
|
||||
btl $0, %ebx
|
||||
jnc LogicalAP0
|
||||
andb $0xFE, %bl
|
||||
jmp Send_SIPI
|
||||
LogicalAP0:
|
||||
orb $0x01, %bl
|
||||
orb $0x01, %bl
|
||||
Send_SIPI:
|
||||
bswapl %ebx // ebx - logical AP's APIC ID
|
||||
bswapl %ebx // ebx - logical AP's APIC ID
|
||||
|
||||
// Fill up the IPI command registers in the Local APIC mapped to default address
|
||||
// and issue SIPI to the other logical processor within this processor die.
|
||||
// Fill up the IPI command registers in the Local APIC mapped to default address
|
||||
// and issue SIPI to the other logical processor within this processor die.
|
||||
Retry_SIPI:
|
||||
movl %ebx, %eax
|
||||
movl $0xFEE00310, %esi
|
||||
movl %eax, (%esi)
|
||||
movl %ebx, %eax
|
||||
movl $0xFEE00310, %esi
|
||||
movl %eax, (%esi)
|
||||
|
||||
// SIPI vector - F900:0000
|
||||
movl $0x000006F9, %eax
|
||||
movl $0xFEE00300, %esi
|
||||
movl %eax, (%esi)
|
||||
// SIPI vector - F900:0000
|
||||
movl $0x000006F9, %eax
|
||||
movl $0xFEE00300, %esi
|
||||
movl %eax, (%esi)
|
||||
|
||||
movl $0x30, %ecx
|
||||
movl $0x30, %ecx
|
||||
SIPI_Delay:
|
||||
pause
|
||||
decl %ecx
|
||||
jnz SIPI_Delay
|
||||
pause
|
||||
decl %ecx
|
||||
jnz SIPI_Delay
|
||||
|
||||
movl (%esi), %eax
|
||||
andl $0x00001000, %eax
|
||||
jnz Retry_SIPI
|
||||
movl (%esi), %eax
|
||||
andl $0x00001000, %eax
|
||||
jnz Retry_SIPI
|
||||
|
||||
// Wait for the Logical AP to complete initialization
|
||||
// Wait for the Logical AP to complete initialization
|
||||
LogicalAP_SIPINotdone:
|
||||
movl $0x250, %ecx
|
||||
rdmsr
|
||||
orl %eax, %eax
|
||||
jz LogicalAP_SIPINotdone
|
||||
movl $0x250, %ecx
|
||||
rdmsr
|
||||
orl %eax, %eax
|
||||
jz LogicalAP_SIPINotdone
|
||||
|
||||
NotHtProcessor:
|
||||
|
||||
#if 1
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
wrmsr
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/*Clear all MTRRs */
|
||||
/* Clear all MTRRs */
|
||||
xorl %edx, %edx
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
|
||||
xorl %edx, %edx
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
clear_fixed_var_mtrr:
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
jz clear_fixed_var_mtrr_out
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
jz clear_fixed_var_mtrr_out
|
||||
|
||||
movl %eax, %ecx
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
movl %eax, %ecx
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
|
||||
jmp clear_fixed_var_mtrr
|
||||
jmp clear_fixed_var_mtrr
|
||||
clear_fixed_var_mtrr_out:
|
||||
|
||||
/* 0x06 is the WB IO type for a given 4k segment.
|
||||
|
|
@ -144,13 +144,13 @@ clear_fixed_var_mtrr_out:
|
|||
*/
|
||||
xorl \reg, \reg
|
||||
.elseif \segs == 1
|
||||
movl $0x06000000, \reg
|
||||
movl $0x06000000, \reg /* WB IO type */
|
||||
.elseif \segs == 2
|
||||
movl $0x06060000, \reg
|
||||
movl $0x06060000, \reg /* WB IO type */
|
||||
.elseif \segs == 3
|
||||
movl $0x06060600, \reg
|
||||
movl $0x06060600, \reg /* WB IO type */
|
||||
.elseif \segs >= 4
|
||||
movl $0x06060606, \reg
|
||||
movl $0x06060606, \reg /* WB IO type */
|
||||
.endif
|
||||
.endm
|
||||
|
||||
|
|
@ -179,170 +179,169 @@ clear_fixed_var_mtrr_out:
|
|||
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
|
||||
#endif
|
||||
|
||||
#if CacheSize > 0x8000
|
||||
/* enable caching for 32K-64K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c0000*/
|
||||
#if CacheSize > 0x8000
|
||||
/* enable caching for 32K-64K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c0000*/
|
||||
simplemask CacheSize, 0x8000
|
||||
wrmsr
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* enable caching for 0-32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
/* enable caching for 0-32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
simplemask CacheSize, 0
|
||||
wrmsr
|
||||
|
||||
#else
|
||||
/* disable cache */
|
||||
movl %cr0, %eax
|
||||
orl $(0x1<<30),%eax
|
||||
movl %eax, %cr0
|
||||
/* disable cache */
|
||||
movl %cr0, %eax
|
||||
orl $(0x1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
|
||||
|
||||
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
movl $0x202, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
movl $0x202, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
|
||||
movl $0x203, %ecx
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
movl $0x203, %ecx
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
|
||||
|
||||
/* enable cache */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
movl %eax, %cr0
|
||||
/* enable cache */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
||||
|
||||
/* Read the range with lodsl*/
|
||||
movl $CacheBase, %esi
|
||||
movl $CacheBase, %esi
|
||||
cld
|
||||
movl $(CacheSize>>2), %ecx
|
||||
rep lodsl
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
rep lodsl
|
||||
|
||||
/* Clear the range */
|
||||
movl $CacheBase, %edi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
movl $CacheBase, %edi
|
||||
movl $(CacheSize >> 2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
|
||||
|
||||
#if 0
|
||||
/* check the cache as ram */
|
||||
movl $CacheBase, %esi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
.xin1:
|
||||
movl %esi, %eax
|
||||
movl %eax, (%esi)
|
||||
decl %ecx
|
||||
je .xout1
|
||||
add $4, %esi
|
||||
jmp .xin1
|
||||
.xout1:
|
||||
movl $CacheBase, %esi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
.xin1:
|
||||
movl %esi, %eax
|
||||
movl %eax, (%esi)
|
||||
decl %ecx
|
||||
je .xout1
|
||||
add $4, %esi
|
||||
jmp .xin1
|
||||
.xout1:
|
||||
|
||||
movl $CacheBase, %esi
|
||||
movl $CacheBase, %esi
|
||||
// movl $(CacheSize>>2), %ecx
|
||||
movl $4, %ecx
|
||||
.xin1x:
|
||||
movl %esi, %eax
|
||||
movl %esi, %eax
|
||||
|
||||
movl $0x4000, %edx
|
||||
movb %ah, %al
|
||||
.testx1:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx1
|
||||
|
||||
movl (%esi), %eax
|
||||
cmpb 0xff, %al
|
||||
je .xin2 /* dont show */
|
||||
movl $0x4000, %edx
|
||||
movb %ah, %al
|
||||
.testx1:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx1
|
||||
|
||||
movl $0x4000, %edx
|
||||
movl (%esi), %eax
|
||||
cmpb 0xff, %al
|
||||
je .xin2 /* dont show */
|
||||
|
||||
movl $0x4000, %edx
|
||||
.testx2:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx2
|
||||
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx2
|
||||
|
||||
.xin2: decl %ecx
|
||||
je .xout1x
|
||||
add $4, %esi
|
||||
jmp .xin1x
|
||||
je .xout1x
|
||||
add $4, %esi
|
||||
jmp .xin1x
|
||||
.xout1x:
|
||||
|
||||
#endif
|
||||
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
|
||||
|
||||
|
||||
movl $(CacheBase+CacheSize-4), %eax
|
||||
movl %eax, %esp
|
||||
movl $(CacheBase + CacheSize - 4), %eax
|
||||
movl %eax, %esp
|
||||
|
||||
/* Load a different set of data segments */
|
||||
#if CONFIG_USE_INIT
|
||||
movw $CACHE_RAM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
movw $CACHE_RAM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
#endif
|
||||
|
||||
lout:
|
||||
|
||||
/* Restore the BIST result */
|
||||
movl %ebp, %eax
|
||||
|
||||
/* We need to set ebp ? No need */
|
||||
movl %esp, %ebp
|
||||
pushl %eax /* bist */
|
||||
call amd64_main
|
||||
pushl %eax /* bist */
|
||||
call amd64_main
|
||||
/* We will not go back */
|
||||
|
||||
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.long 0x000 /* NULL, end of table */
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.long 0x000 /* NULL, end of table */
|
||||
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
||||
.align 0x1000
|
||||
.code16
|
||||
.align 0x1000
|
||||
.code16
|
||||
.global LogicalAP_SIPI
|
||||
LogicalAP_SIPI:
|
||||
// cr0 register is shared among the logical processors;
|
||||
// so clear CD & NW bits so that the BSP's cr0 register
|
||||
// controls the cache behavior
|
||||
// Note: The cache behavior is determined by "OR" result
|
||||
// of the cr0 registers of the logical processors
|
||||
// cr0 register is shared among the logical processors;
|
||||
// so clear CD & NW bits so that the BSP's cr0 register
|
||||
// controls the cache behavior
|
||||
// Note: The cache behavior is determined by "OR" result
|
||||
// of the cr0 registers of the logical processors
|
||||
|
||||
movl %cr0, %eax
|
||||
andl $0x9FFFFFFF, %eax
|
||||
movl %eax, %cr0
|
||||
movl %cr0, %eax
|
||||
andl $0x9FFFFFFF, %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
finit
|
||||
finit
|
||||
|
||||
// Set the semaphore to indicate the Logical AP is done
|
||||
// with CAR specific initialization
|
||||
movl $0x250, %ecx
|
||||
movl $0x06, %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
// Set the semaphore to indicate the Logical AP is done
|
||||
// with CAR specific initialization
|
||||
movl $0x250, %ecx
|
||||
movl $0x06, %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
|
||||
// Halt this AP
|
||||
cli
|
||||
// Halt this AP
|
||||
cli
|
||||
Halt_LogicalAP:
|
||||
hlt
|
||||
jmp Halt_LogicalAP
|
||||
.code32
|
||||
hlt
|
||||
jmp Halt_LogicalAP
|
||||
.code32
|
||||
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
|
||||
.CacheAsRam_out:
|
||||
|
|
|
|||
Loading…
Reference in New Issue