White space and comment fixes for cache_as_ram.inc files so it's easier to spot
differences. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Myles Watson
parent
35ed0e7ea3
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707fad0508
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@ -253,7 +253,7 @@ clear_fixed_var_mtrr_out:
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#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
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/* disable cache */
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movl %cr0, %eax
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orl $(1 << 30),%eax
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orl $(0x1 << 30), %eax
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movl %eax, %cr0
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#endif
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@ -317,6 +317,7 @@ fam10_end_part1:
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movl $CacheBase, %esi
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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@ -52,6 +52,7 @@ CacheAsRam:
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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@ -82,16 +83,15 @@ clear_fixed_var_mtrr_out:
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/* MTRRPhysBase */
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
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movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x203, %ecx
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movl $0x0000000f,%edx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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@ -99,7 +99,7 @@ clear_fixed_var_mtrr_out:
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wrmsr
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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@ -111,7 +111,7 @@ clear_fixed_var_mtrr_out:
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize>>2), %ecx
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movl $(CacheSize >> 2), %ecx
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/* 0x5c5c5c5c is a memory test pattern.
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* TODO: Check if everything works with the zero pattern as well. */
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@ -128,7 +128,7 @@ clear_fixed_var_mtrr_out:
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* "no fill" mode, which is not compatible with general CAR code.
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*/
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movl $(CacheBase+CacheSize-4), %eax
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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#ifdef CARTEST
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@ -153,6 +153,7 @@ testok: movb $0x40,%al
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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@ -115,10 +115,10 @@ NotHtProcessor:
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wrmsr
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#endif
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/*Clear all MTRRs */
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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@ -144,13 +144,13 @@ clear_fixed_var_mtrr_out:
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*/
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xorl \reg, \reg
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.elseif \segs == 1
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movl $0x06000000, \reg
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movl $0x06000000, \reg /* WB IO type */
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.elseif \segs == 2
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movl $0x06060000, \reg
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movl $0x06060000, \reg /* WB IO type */
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.elseif \segs == 3
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movl $0x06060600, \reg
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movl $0x06060600, \reg /* WB IO type */
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.elseif \segs >= 4
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movl $0x06060606, \reg
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movl $0x06060606, \reg /* WB IO type */
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.endif
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.endm
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@ -194,7 +194,7 @@ clear_fixed_var_mtrr_out:
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#else
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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orl $(0x1 << 30), %eax
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movl %eax, %cr0
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#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
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@ -216,7 +216,7 @@ clear_fixed_var_mtrr_out:
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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@ -224,12 +224,12 @@ clear_fixed_var_mtrr_out:
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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movl $(CacheSize>>2), %ecx
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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@ -280,7 +280,7 @@ clear_fixed_var_mtrr_out:
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#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
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movl $(CacheBase+CacheSize-4), %eax
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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@ -292,16 +292,15 @@ clear_fixed_var_mtrr_out:
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#endif
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lout:
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call amd64_main
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/* We will not go back */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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