Clean up vt8235_early_smbus a bit.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
85793c2b3f
commit
708743379a
|
@ -30,60 +30,42 @@ static void enable_smbus(void)
|
||||||
device_t dev;
|
device_t dev;
|
||||||
unsigned char c;
|
unsigned char c;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
/* Power management controller */
|
/* Power management controller */
|
||||||
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0);
|
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
|
||||||
|
PCI_DEVICE_ID_VIA_8235), 0);
|
||||||
|
|
||||||
if (dev == PCI_DEV_INVALID) {
|
if (dev == PCI_DEV_INVALID) {
|
||||||
die("SMBUS controller not found\r\n");
|
die("SMBUS controller not found\r\n");
|
||||||
}
|
}
|
||||||
pci_write_config8(dev, 0xd2, (0x4 << 1 ));
|
|
||||||
|
|
||||||
// set IO base address to SMBUS_IO_BASE
|
// set IO base address to SMBUS_IO_BASE
|
||||||
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE);
|
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
|
||||||
|
|
||||||
// Enable SMBus
|
// Enable SMBus
|
||||||
pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
|
pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
|
||||||
|
|
||||||
// Enable RTC
|
|
||||||
pci_write_config8(dev,0x51,0x04);
|
|
||||||
|
|
||||||
/* make it work for I/O ...
|
/* make it work for I/O ...
|
||||||
*/
|
*/
|
||||||
pci_write_config16(dev, 4, 1);
|
pci_write_config16(dev, 4, 1);
|
||||||
|
|
||||||
|
|
||||||
/* tell the world we're alive - make power led flash during bios execution */
|
|
||||||
pci_write_config8(dev,0x94,0xb2);
|
|
||||||
|
|
||||||
|
|
||||||
/* FIX for half baud rate problem */
|
/* FIX for half baud rate problem */
|
||||||
/* let clocks and the like settle */
|
/* let clocks and the like settle */
|
||||||
/* as yet arbitrary count - 1000 is too little 5000 works */
|
/* as yet arbitrary count - 1000 is too little 5000 works */
|
||||||
for(i = 0 ; i < 5000 ; i++)
|
for(i = 0 ; i < 5000 ; i++)
|
||||||
outb(0x80,0x80);
|
outb(0x80,0x80);
|
||||||
|
|
||||||
/* southbridge doesn't seem to like to do much untill after this delay, so set up
|
/*
|
||||||
* the flashing power LED again */
|
* The VT1211 serial port needs 48 mhz clock, on power up it is getting
|
||||||
pci_write_config8(dev,0x94,0xb2);
|
* only 24 mhz, there is some mysterious device on the smbus that can
|
||||||
|
* fix this...this code below does it.
|
||||||
/* The VT1211 serial port needs 48 mhz clock, on power up it is getting
|
* */
|
||||||
only 24 mhz, there is some mysterious device on the smbus that can
|
|
||||||
fix this...this code below does it. */
|
|
||||||
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
|
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
|
||||||
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
|
|
||||||
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
|
|
||||||
outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
|
|
||||||
for( ;;) {
|
|
||||||
c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
|
|
||||||
if ((c & 1) == 0)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
|
outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
|
||||||
outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
|
outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
|
||||||
outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
|
outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
|
||||||
outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
|
outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
|
||||||
|
|
||||||
|
|
||||||
for (;;) {
|
for (;;) {
|
||||||
c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
|
c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
|
||||||
if ((c & 1) == 0)
|
if ((c & 1) == 0)
|
||||||
|
|
Loading…
Reference in New Issue