diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h
index f8c1121f1a..132a5ce353 100644
--- a/src/arch/ppc64/include/arch/io.h
+++ b/src/arch/ppc64/include/arch/io.h
@@ -5,31 +5,63 @@
 
 #include <stdint.h>
 
+/* Set MSB to 1 to ignore HRMOR */
+#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
+#define LPCHC_IO_SPACE 0xD0010000
+#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
+
+/* Enforce In-order Execution of I/O */
+static inline void eieio(void)
+{
+	asm volatile("eieio" ::: "memory");
+}
+
 static inline void outb(uint8_t value, uint16_t port)
 {
+	asm volatile("stbcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
 }
 
 static inline void outw(uint16_t value, uint16_t port)
 {
+	asm volatile("sthcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
 }
 
 static inline void outl(uint32_t value, uint16_t port)
 {
+	asm volatile("stwcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
 }
 
 static inline uint8_t inb(uint16_t port)
 {
-	return 0;
+	uint8_t buffer;
+	asm volatile("lbzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
+	return buffer;
 }
 
 static inline uint16_t inw(uint16_t port)
 {
-	return 0;
+	uint16_t buffer;
+	asm volatile("lhzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
+	return buffer;
 }
 
 static inline uint32_t inl(uint16_t port)
 {
-	return 0;
+	uint32_t buffer;
+	asm volatile("lwzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
+	eieio();
+	return buffer;
+}
+
+static inline void report_istep(uint8_t step, uint8_t substep)
+{
+	outb(step, 0x81);
+	outb(substep, 0x82);
 }
 
 #endif