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- Ensure every copy of Options.lb uses: 

CROSS_COMPILE
  CC
  HOSTCC
  OBJCOPY


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2004-11-05 10:48:04 +00:00
parent d0805e0b55
commit 709850a21b
30 changed files with 261 additions and 157 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/Iwill/DK8S2/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
@ -161,7 +163,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
#default CC="gcc"
#default CC="$(CROSS_COMPILE)gcc -m32"
#default HOSTCC="gcc"
##

8
src/mainboard/Iwill/DK8X/Options.lb
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@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
@ -160,7 +162,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
#default CC="gcc"
#default CC="$(CROSS_COMPILE)gcc -m32"
#default HOSTCC="gcc"
##

8
src/mainboard/amd/quartet/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
@ -157,7 +159,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

3
src/mainboard/amd/quartet/auto.c
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@ -154,7 +154,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* quartet does not want the default */
/* quartet does not want the default */
#include "resourcemap.c"
#define RC0 ((1<<1)<<8)
#define RC1 ((1<<2)<<8)

9
src/mainboard/amd/serenade/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -43,7 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -157,7 +158,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/amd/solo/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
@ -157,7 +159,8 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

8
src/mainboard/arima/hdama/Options.lb
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@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +165,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

10
src/mainboard/densitron/dpx114/Options.lb
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@ -27,6 +27,10 @@ uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@ -89,4 +93,10 @@ default _RAMBASE = 0x00004000
default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
end

10
src/mainboard/digitallogic/adl855pc/Options.lb
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@ -27,6 +27,10 @@ uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@ -90,6 +94,12 @@ default _RAMBASE = 0x00004000
default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
end

27
src/mainboard/embeddedplanet/ep405pc/Config.lb
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@ -2,33 +2,6 @@
## Config file for the Embedded Planet EP405PC Computing Engine
##
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses TTYS0_BASE
uses _IO_BASE
##
## Set PCI configuration register addresses
##
default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004
##
## Set PCI/ISA I/O and memory base address
##
default ISA_IO_BASE=0xe8000000
default ISA_MEM_BASE=0x80000000
default _IO_BASE=ISA_IO_BASE
##
## HACK ALERT: the UART0 registers are not in the PCI I/O address space
## but both IDE and UART use the same routines for I/O (inb/outb). To get
## around this we set TTYSO_BASE to the difference between the two.
##
default TTYS0_BASE=0xef600300-ISA_IO_BASE
##
## Early board initialization, called from ppc_main()
##

35
src/mainboard/embeddedplanet/ep405pc/Options.lb Normal file
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@ -0,0 +1,35 @@
##
## Config file for the Embedded Planet EP405PC Computing Engine
##
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses TTYS0_BASE
uses _IO_BASE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
##
## Set PCI configuration register addresses
##
default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004
##
## Set PCI/ISA I/O and memory base address
##
default ISA_IO_BASE=0xe8000000
default ISA_MEM_BASE=0x80000000
default _IO_BASE=ISA_IO_BASE
##
## HACK ALERT: the UART0 registers are not in the PCI I/O address space
## but both IDE and UART use the same routines for I/O (inb/outb). To get
## around this we set TTYSO_BASE to the difference between the two.
##
default TTYS0_BASE=0xef600300-ISA_IO_BASE

8
src/mainboard/emulation/qemu-i386/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -45,6 +43,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -159,7 +161,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

8
src/mainboard/ibm/e325/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
@ -159,7 +161,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

23
src/mainboard/motorola/sandpoint/Config.lb
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@ -2,29 +2,6 @@
## Config file for the Motorola Sandpoint III development system.
## Note that this has only been tested with the Altimus 7410 PMC.
##
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_SANDPOINT_TALUS
uses CONFIG_SANDPOINT_UNITY
uses CONFIG_SANDPOINT_VALIS
uses CONFIG_SANDPOINT_GYRUS
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses PNP_CFGADDR
uses PNP_CFGDATA
uses _IO_BASE
##
## Set memory map
##
default ISA_IO_BASE=0xfe000000
default ISA_MEM_BASE=0xfd000000
default PCIC0_CFGADDR=0xfec00000
default PCIC0_CFGDATA=0xfee00000
default PNP_CFGADDR=0x15c
default PNP_CFGDATA=0x15d
default _IO_BASE=ISA_IO_BASE
##
## Early board initialization, called from ppc_main()

27
src/mainboard/motorola/sandpoint/Options.lb Normal file
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@ -0,0 +1,27 @@
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_SANDPOINT_TALUS
uses CONFIG_SANDPOINT_UNITY
uses CONFIG_SANDPOINT_VALIS
uses CONFIG_SANDPOINT_GYRUS
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses PNP_CFGADDR
uses PNP_CFGDATA
uses _IO_BASE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
##
## Set memory map
##
default ISA_IO_BASE=0xfe000000
default ISA_MEM_BASE=0xfd000000
default PCIC0_CFGADDR=0xfec00000
default PCIC0_CFGDATA=0xfee00000
default PNP_CFGADDR=0x15c
default PNP_CFGDATA=0x15d
default _IO_BASE=ISA_IO_BASE

9
src/mainboard/newisys/khepri/Options.lb
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@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -43,7 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -157,7 +158,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc -m32"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

28
src/mainboard/totalimpact/briq/Config.lb
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@ -2,34 +2,6 @@
## Config file for the Total Impact briQ
##
uses TTYS0_DIV
uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses _IO_BASE
##
## Set memory map
##
default ISA_IO_BASE=0x80000000
default ISA_MEM_BASE=0xc0000000
default PCIC0_CFGADDR=0xff5f8000
default PCIC0_CFGDATA=0xff5f8010
default _IO_BASE=ISA_IO_BASE
##
## The briQ uses weird clocking, 4 = 115200
##
default TTYS0_DIV=4
##
## Set UART base address
##
default TTYS0_BASE=0x3f8
##
## Early board initialization, called from ppc_main()
##

35
src/mainboard/totalimpact/briq/Options.lb Normal file
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@ -0,0 +1,35 @@
##
## Config file for the Total Impact briQ
##
uses TTYS0_DIV
uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses _IO_BASE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
##
## Set memory map
##
default ISA_IO_BASE=0x80000000
default ISA_MEM_BASE=0xc0000000
default PCIC0_CFGADDR=0xff5f8000
default PCIC0_CFGDATA=0xff5f8010
default _IO_BASE=ISA_IO_BASE
##
## The briQ uses weird clocking, 4 = 115200
##
default TTYS0_DIV=4
##
## Set UART base address
##
default TTYS0_BASE=0x3f8

8
src/mainboard/tyan/s2735/Options.lb
View File

@ -35,8 +35,6 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,6 +45,10 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -169,7 +171,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

8
src/mainboard/tyan/s2850/Options.lb
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@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -162,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s2875/Options.lb
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@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s2880/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s2881/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s2882/Options.lb
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@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

10
src/mainboard/tyan/s2885/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,11 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +165,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s4880/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

9
src/mainboard/tyan/s4882/Options.lb
View File

@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
###
### Build options
@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="gcc"
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##

11
src/mainboard/via/epia-m/Options.lb
View File

@ -28,6 +28,10 @@ uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses HAVE_ACPI_TABLES
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@ -90,5 +94,12 @@ default _RAMBASE = 0x00004000
default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
end

12
src/mainboard/via/epia/Options.lb
View File

@ -27,6 +27,10 @@ uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@ -90,5 +94,13 @@ default _RAMBASE = 0x00004000
default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
end

40
util/abuild/abuild.sh
View File

@ -68,8 +68,8 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
# not supported yet
# option LD="CROSSLD"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
romimage "normal"
option USE_FALLBACK_IMAGE=0
@ -91,7 +91,8 @@ EOF
-e s,MAINBOARD,$MAINBOARD,g \
-e s,PAYLOAD,$PAYLOAD,g \
-e s,CROSSCC,"$CC",g \
-e s,CROSSLD,"$LD",g \
-e s,CROSS_PREFIX,"$CROSS_COMPILE",g \
-e s,CROSS_HOSTCC,"$HOSTCC",g \
> $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
echo " ok"
}
@ -185,7 +186,8 @@ function build_target
# default setting
CC="gcc"
LD="ld"
HOSTCC="gcc"
CROSS_COMPILE=""
echo -n "Processing mainboard/$VENDOR/$MAINBOARD"
@ -203,6 +205,14 @@ function build_target
found_crosscompiler=true
echo " ($TARCH: subset of $ARCH)"
fi
if [ "$found_crosscompiler" == "false" -a "$TARCH" == ppc ] ;then
for prefix in powerpc-linux- ; do
if ${prefix}gcc --version > /dev/null 2> /dev/null ; then
found_crosscompiler=true
CROSS_COMPILE=$prefix
fi
done
fi
# TBD: look for suitable cross compiler suite
# cross-$TARCH-gcc and cross-$TARCH-ld
@ -211,6 +221,8 @@ function build_target
if [ $found_crosscompiler == "false" ]; then
echo " ($TARCH: skipped, we're $ARCH)"
return 0
else
echo " ($TARCH: ok)"
fi
fi
@ -283,16 +295,16 @@ fi
echo "LBROOT=$LBROOT"
if [ "$target" != "" ]; then
# build a single board
VENDOR=`echo $target|tr -d \'|cut -f1 -d/`
MAINBOARD=`echo $target|tr -d \'|cut -f2 -d/`
build_target $VENDOR $MAINBOARD
# build a single board
VENDOR=`echo $target|tr -d \'|cut -f1 -d/`
MAINBOARD=`echo $target|tr -d \'|cut -f2 -d/`
build_target $VENDOR $MAINBOARD
else
# build all boards per default
for VENDOR in $( vendors ); do
for MAINBOARD in $( mainboards $VENDOR ); do
build_target $VENDOR $MAINBOARD
done
done
# build all boards per default
for VENDOR in $( vendors ); do
for MAINBOARD in $( mainboards $VENDOR ); do
build_target $VENDOR $MAINBOARD
done
done
fi