GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/starlabs/labtop: Reconfigure CNVi GPIOs 

Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2022-01-04 11:09:41 +00:00 committed by Martin Roth - Personal
parent ad58a188e8
commit 70a1ef0716
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/starlabs/labtop/variants/tgl/gpio.c
View File

@ -279,15 +279,15 @@ const struct pad_config gpio_table[] = {
/* F0: CNV_BRI_DT_BT_UART0_RTS_R */ /* F0: CNV_BRI_DT_BT_UART0_RTS_R */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* F1: CNV_BRI_RSP_BT_UART0_RX_R */ /* F1: CNV_BRI_RSP_BT_UART0_RX_R */
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
/* F2: CNV_RGI_DT_BT_UART0_TX_R */ /* F2: CNV_RGI_DT_BT_UART0_TX_R */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
/* F3: CNV_RGI_RSP_BT_UART0_CTS */ /* F3: CNV_RGI_RSP_BT_UART0_CTS */
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
/* F4: Not Connected */ /* F4: Not Connected */
PAD_NC(GPP_F4, NONE), PAD_NC(GPP_F4, NONE),
/* F5: GPPC_F5_MODEM_CLKREQ */ /* F5: GPPC_F5_MODEM_CLKREQ */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), PAD_NC(GPP_F5, NONE),
/* F6: Not Connected */ /* F6: Not Connected */
PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F6, NONE),
/* F7: BIOS_REC */ /* F7: BIOS_REC */