soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Rename from jasperlake to elkhartlake 2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op) Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tan, Lean Sheng
Patrick Georgi
parent
05dfe3177d
commit
70a2ddc5ac
12 changed files with 1048 additions and 0 deletions
137
src/soc/intel/elkhartlake/acpi/gpio.asl
Normal file
137
src/soc/intel/elkhartlake/acpi/gpio.asl
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@ -0,0 +1,137 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/gpio.h>
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#include <soc/gpio_defs.h>
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#include <soc/intel/common/acpi/gpio.asl>
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#include <soc/irq.h>
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#include <soc/pcr_ids.h>
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Device (GPIO)
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{
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Name (_HID, CROS_GPIO_NAME)
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Name (_UID, 0)
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Name (_DDN, "GPIO Controller")
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Memory32Fixed (ReadWrite, 0, 0, COM5)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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{ GPIO_IRQ14 }
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})
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
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CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
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BAS0 = ^^PCRB (PID_GPIOCOM0)
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LEN0 = GPIO_BASE_SIZE
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/* GPIO Community 1 */
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CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
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CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
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BAS1 = ^^PCRB (PID_GPIOCOM1)
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LEN1 = GPIO_BASE_SIZE
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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BAS2 = ^^PCRB (PID_GPIOCOM2)
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LEN2 = GPIO_BASE_SIZE
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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BAS4 = ^^PCRB (PID_GPIOCOM4)
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LEN4 = GPIO_BASE_SIZE
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/* GPIO Community 5 */
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CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
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CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
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BAS5 = ^^PCRB (PID_GPIOCOM5)
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LEN5 = GPIO_BASE_SIZE
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Return (RBUF)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF)
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}
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}
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/*
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* Get GPIO DW0 Address
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* Arg0 - GPIO Number
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*/
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
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{
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Local0 = PID_GPIOCOM0
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Local1 = Arg0 - GPIO_COM0_START
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}
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/* GPIO Community 1 */
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If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
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{
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Local0 = PID_GPIOCOM1
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Local1 = Arg0 - GPIO_COM1_START
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}
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/* GPIO Community 2 */
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If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
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{
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Local0 = PID_GPIOCOM2
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Local1 = Arg0 - GPIO_COM2_START
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}
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/* GPIO Community 4 */
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If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
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{
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Local0 = PID_GPIOCOM4
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Local1 = Arg0 - GPIO_COM4_START
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}
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/* GPIO Community 05*/
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If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
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{
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Local0 = PID_GPIOCOM5
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Local1 = Arg0 - GPIO_COM5_START
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}
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Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
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Return (Local2)
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}
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/*
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* Return PCR Port ID of GPIO Communities
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*
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* Arg0: GPIO Community (0-5)
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*/
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Method (GPID, 1, Serialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (COMM_0) {
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Local0 = PID_GPIOCOM0
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}
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Case (COMM_1) {
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Local0 = PID_GPIOCOM1
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}
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Case (COMM_2) {
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Local0 = PID_GPIOCOM2
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}
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Case (COMM_4) {
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Local0 = PID_GPIOCOM4
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}
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Case (COMM_5) {
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Local0 = PID_GPIOCOM5
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}
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Default {
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Return (0)
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}
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}
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Return (Local0)
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}
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14
src/soc/intel/elkhartlake/acpi/pch_glan.asl
Normal file
14
src/soc/intel/elkhartlake/acpi/pch_glan.asl
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel Gigabit Ethernet Controller 0:1f.6 */
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Device (GLAN)
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{
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Name (_ADR, 0x001f0006)
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Name (_S0W, 3)
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Name (_PRW, Package() {GPE0_PME_B0, 4})
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Method (_DSW, 3) {}
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}
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68
src/soc/intel/elkhartlake/acpi/pch_hda.asl
Normal file
68
src/soc/intel/elkhartlake/acpi/pch_hda.asl
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@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Audio Controller - Device 31, Function 3 */
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Device (HDAS)
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{
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Name (_ADR, 0x001f0003)
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Name (_DDN, "Audio Controller")
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Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
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/* Device is D3 wake capable */
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Name (_S0W, 3)
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/* NHLT Table Address populated from GNVS values */
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Name (NBUF, ResourceTemplate () {
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QWordMemory (ResourceConsumer, PosDecode, MinFixed,
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MaxFixed, NonCacheable, ReadOnly,
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0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
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})
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (Arg0 == ^UUID) {
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/*
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* Function 0: Function Support Query
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* Returns a bitmask of functions supported.
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*/
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If (Arg2 == Zero) {
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/*
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* NHLT Query only supported for revision 1 and
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* if NHLT address and length are set in NVS.
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*/
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If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) {
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Return (Buffer (One) { 0x03 })
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} Else {
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Return (Buffer (One) { 0x01 })
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}
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}
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/*
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* Function 1: Query NHLT memory address used by
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* Intel Offload Engine Driver to discover any non-HDA
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* devices that are supported by the DSP.
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*
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* Returns a pointer to NHLT table in memory.
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*/
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If (Arg2 == One) {
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CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
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CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
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CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
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NBAS = NHLA
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NMAS = NHLA
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NLEN = NHLL
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Return (NBUF)
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}
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}
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Return (Buffer (One) { 0x00 })
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}
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}
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112
src/soc/intel/elkhartlake/acpi/pci_irqs.asl
Normal file
112
src/soc/intel/elkhartlake/acpi/pci_irqs.asl
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <soc/irq.h>
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Name (PICP, Package () {
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Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 },
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Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 },
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Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 },
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Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 },
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Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
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/* SA GNA Device */
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Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 },
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})
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Name (PICN, Package () {
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Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 },
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Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 },
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Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 },
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Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 },
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Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 },
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 },
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})
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Method (_PRT)
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{
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If (PICM) {
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Return (^PICP)
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} Else {
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Return (^PICN)
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}
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}
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301
src/soc/intel/elkhartlake/acpi/pcie.asl
Normal file
301
src/soc/intel/elkhartlake/acpi/pcie.asl
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel PCH PCIe support */
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Method (IRQM, 1, Serialized) {
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/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
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Name (IQAA, Package () {
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Package () { 0x0000ffff, 0, 0, 16 },
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Package () { 0x0000ffff, 1, 0, 17 },
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Package () { 0x0000ffff, 2, 0, 18 },
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Package () { 0x0000ffff, 3, 0, 19 } })
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Name (IQAP, Package () {
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Package () { 0x0000ffff, 0, 0, 11 },
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Package () { 0x0000ffff, 1, 0, 10 },
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Package () { 0x0000ffff, 2, 0, 11 },
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Package () { 0x0000ffff, 3, 0, 11 } })
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/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
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Name (IQBA, Package () {
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Package () { 0x0000ffff, 0, 0, 17 },
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Package () { 0x0000ffff, 1, 0, 18 },
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Package () { 0x0000ffff, 2, 0, 19 },
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Package () { 0x0000ffff, 3, 0, 16 } })
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Name (IQBP, Package () {
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Package () { 0x0000ffff, 0, 0, 10 },
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Package () { 0x0000ffff, 1, 0, 11 },
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Package () { 0x0000ffff, 2, 0, 11 },
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Package () { 0x0000ffff, 3, 0, 11 } })
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/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
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Name (IQCA, Package () {
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Package () { 0x0000ffff, 0, 0, 18 },
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Package () { 0x0000ffff, 1, 0, 19 },
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Package () { 0x0000ffff, 2, 0, 16 },
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Package () { 0x0000ffff, 3, 0, 17 } })
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Name (IQCP, Package () {
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Package () { 0x0000ffff, 0, 0, 11 },
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Package () { 0x0000ffff, 1, 0, 11 },
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Package () { 0x0000ffff, 2, 0, 11 },
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Package () { 0x0000ffff, 3, 0, 10 } })
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/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
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Name (IQDA, Package () {
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Package () { 0x0000ffff, 0, 0, 19 },
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Package () { 0x0000ffff, 1, 0, 16 },
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Package () { 0x0000ffff, 2, 0, 17 },
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Package () { 0x0000ffff, 3, 0, 18 } })
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Name (IQDP, Package () {
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Package () { 0x0000ffff, 0, 0, 11 },
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Package () { 0x0000ffff, 1, 0, 11 },
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Package () { 0x0000ffff, 2, 0, 10 },
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Package () { 0x0000ffff, 3, 0, 11 } })
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Switch (ToInteger (Arg0))
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{
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Case (Package () { 1, 5, 9, 13 }) {
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If (PICM) {
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Return (IQAA)
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} Else {
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Return (IQAP)
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}
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}
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Case (Package () { 2, 6, 10, 14 }) {
|
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If (PICM) {
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Return (IQBA)
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} Else {
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Return (IQBP)
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}
|
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}
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Case (Package () { 3, 7, 11, 15 }) {
|
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If (PICM) {
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Return (IQCA)
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} Else {
|
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Return (IQCP)
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}
|
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}
|
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Case (Package () { 4, 8, 12, 16 }) {
|
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If (PICM) {
|
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Return (IQDA)
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} Else {
|
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Return (IQDP)
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}
|
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}
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Default {
|
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If (PICM) {
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Return (IQDA)
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} Else {
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Return (IQDP)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP01)
|
||||
{
|
||||
Name (_ADR, 0x001C0000)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP02)
|
||||
{
|
||||
Name (_ADR, 0x001C0001)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP03)
|
||||
{
|
||||
Name (_ADR, 0x001C0002)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP04)
|
||||
{
|
||||
Name (_ADR, 0x001C0003)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP05)
|
||||
{
|
||||
Name (_ADR, 0x001C0004)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP06)
|
||||
{
|
||||
Name (_ADR, 0x001C0005)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP07)
|
||||
{
|
||||
Name (_ADR, 0x001C0006)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP08)
|
||||
{
|
||||
Name (_ADR, 0x001C0007)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP09)
|
||||
{
|
||||
Name (_ADR, 0x001D0000)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP10)
|
||||
{
|
||||
Name (_ADR, 0x001D0001)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP11)
|
||||
{
|
||||
Name (_ADR, 0x001D0002)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP12)
|
||||
{
|
||||
Name (_ADR, 0x001D0003)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
20
src/soc/intel/elkhartlake/acpi/platform.asl
Normal file
20
src/soc/intel/elkhartlake/acpi/platform.asl
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Enable ACPI _SWS methods */
|
||||
#include <soc/intel/common/acpi/acpi_wake_source.asl>
|
||||
/* Generic indicator for sleep state */
|
||||
#include <soc/intel/common/acpi/platform.asl>
|
||||
|
||||
/*
|
||||
* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
|
||||
Method (_PIC, 1)
|
||||
{
|
||||
/* Remember the OS' IRQ routing choice. */
|
||||
PICM = Arg0
|
||||
}
|
||||
19
src/soc/intel/elkhartlake/acpi/pmc.asl
Normal file
19
src/soc/intel/elkhartlake/acpi/pmc.asl
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/iomap.h>
|
||||
|
||||
Scope (\_SB.PCI0) {
|
||||
|
||||
Device (PMC)
|
||||
{
|
||||
Name (_HID, "INTC1026")
|
||||
Name (_DDN, "Intel(R) Elkhart Lake IPC Controller")
|
||||
/*
|
||||
* PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
|
||||
* 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
|
||||
*/
|
||||
Name (_CRS, ResourceTemplate () {
|
||||
Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
|
||||
})
|
||||
}
|
||||
}
|
||||
193
src/soc/intel/elkhartlake/acpi/scs.asl
Normal file
193
src/soc/intel/elkhartlake/acpi/scs.asl
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
Scope (\_SB.PCI0) {
|
||||
|
||||
/*
|
||||
* Clear register 0x1C20/0x4820
|
||||
* Arg0 - PCR Port ID
|
||||
*/
|
||||
Method(SCSC, 1, Serialized)
|
||||
{
|
||||
PCRA (Arg0, 0x1C20, 0x0)
|
||||
PCRA (Arg0, 0x4820, 0x0)
|
||||
}
|
||||
|
||||
/* EMMC */
|
||||
Device(PEMC) {
|
||||
Name(_ADR, 0x001A0000)
|
||||
Name (_DDN, "eMMC Controller")
|
||||
Name (TEMP, 0)
|
||||
|
||||
OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
|
||||
Field(SCSR, WordAcc, NoLock, Preserve) {
|
||||
Offset (0x84), /* PMECTRLSTATUS */
|
||||
PMCR, 16,
|
||||
Offset (0xA2), /* PG_CONFIG */
|
||||
, 2,
|
||||
PGEN, 1, /* PG_ENABLE */
|
||||
}
|
||||
|
||||
Method(_INI) {
|
||||
/* Clear register 0x1C20/0x4820 */
|
||||
SCSC (PID_EMMC)
|
||||
}
|
||||
|
||||
Method(_PS0, 0, Serialized) {
|
||||
Stall (50) // Sleep 50 us
|
||||
|
||||
PGEN = 0 // Disable PG
|
||||
|
||||
/* Clear register 0x1C20/0x4820 */
|
||||
SCSC (PID_EMMC)
|
||||
|
||||
/* Set Power State to D0 */
|
||||
PMCR = PMCR & 0xFFFC
|
||||
TEMP = PMCR
|
||||
}
|
||||
|
||||
Method(_PS3, 0, Serialized) {
|
||||
PGEN = 1 // Enable PG
|
||||
|
||||
/* Set Power State to D3 */
|
||||
PMCR = PMCR | 0x0003
|
||||
TEMP = PMCR
|
||||
}
|
||||
|
||||
Device (CARD)
|
||||
{
|
||||
Name (_ADR, 0x00000008)
|
||||
Method (_RMV, 0, NotSerialized)
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* SD CARD */
|
||||
Device (SDXC)
|
||||
{
|
||||
Name (_ADR, 0x00140005)
|
||||
Name (_DDN, "SD Controller")
|
||||
Name (TEMP, 0)
|
||||
Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
|
||||
|
||||
OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
|
||||
Field (SDPC, WordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x84), /* PMECTRLSTATUS */
|
||||
PMCR, 16,
|
||||
Offset (0xA2), /* PG_CONFIG */
|
||||
, 2,
|
||||
PGEN, 1, /* PG_ENABLE */
|
||||
}
|
||||
|
||||
/*
|
||||
* _DSM x86 Device Specific Method
|
||||
* Arg0: UUID Unique function identifier
|
||||
* Arg1: Integer Revision Level
|
||||
* Arg2: Integer Function Index (0 = Return Supported Functions)
|
||||
* Arg3: Package Parameters
|
||||
*/
|
||||
Method (_DSM, 4)
|
||||
{
|
||||
If (Arg0 == DSUU) {
|
||||
/* Check the revision */
|
||||
If (Arg1 >= 0) {
|
||||
/*
|
||||
* Function Index 0 the return value is a buffer containing
|
||||
* one bit for each function index, starting with zero.
|
||||
* Bit 0 - Indicates whether there is support for any
|
||||
* functions other than function 0.
|
||||
* Bit 1 - Indicates support to clear power control register
|
||||
* Bit 2 - Indicates support to set power control register
|
||||
* Bit 3 - Indicates support to set 1.8V signalling
|
||||
* Bit 4 - Indicates support to set 3.3V signalling
|
||||
* Bit 5 - Indicates support for HS200 mode
|
||||
* Bit 6 - Indicates support for HS400 mode
|
||||
* Bit 9 - Indicates eMMC I/O Driver Strength
|
||||
*/
|
||||
/*
|
||||
* For SD we have to support functions to
|
||||
* set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
|
||||
*/
|
||||
If (Arg2 == 0) {
|
||||
Return (Buffer () { 0x19 })
|
||||
}
|
||||
/*
|
||||
* Function Index 3: Set 1.8v signalling.
|
||||
* We put a sleep of 100ms in this method to
|
||||
* work around a known issue with detecting
|
||||
* UHS SD card on PCH. This is to compensate
|
||||
* for the SD VR slowness.
|
||||
*/
|
||||
If (Arg2 == 3) {
|
||||
Sleep (100)
|
||||
Return(Buffer () { 0x00 })
|
||||
}
|
||||
/*
|
||||
* Function Index 4: Set 3.3v signalling.
|
||||
* We put a sleep of 100ms in this method to
|
||||
* work around a known issue with detecting
|
||||
* UHS SD card on PCH. This is to compensate
|
||||
* for the SD VR slowness.
|
||||
*/
|
||||
If (Arg2 == 4) {
|
||||
Sleep (100)
|
||||
Return(Buffer () { 0x00 })
|
||||
}
|
||||
}
|
||||
}
|
||||
Return(Buffer() { 0x0 })
|
||||
}
|
||||
|
||||
Method(_INI)
|
||||
{
|
||||
/* Clear register 0x1C20/0x4820 */
|
||||
SCSC (PID_SDX)
|
||||
}
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
PGEN = 0 /* Disable PG */
|
||||
|
||||
/* Clear register 0x1C20/0x4820 */
|
||||
SCSC (PID_SDX)
|
||||
|
||||
/* Set Power State to D0 */
|
||||
PMCR = PMCR & 0xFFFC
|
||||
TEMP = PMCR
|
||||
|
||||
/* Change pad mode to Native */
|
||||
GPMO(SD_PWR_EN_PIN, 0x1)
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
PGEN = 1 /* Enable PG */
|
||||
|
||||
/* Set Power State to D3 */
|
||||
PMCR = PMCR | 0x0003
|
||||
TEMP = PMCR
|
||||
|
||||
/* Change pad mode to GPIO control */
|
||||
GPMO(SD_PWR_EN_PIN, 0x0)
|
||||
|
||||
/* Enable Tx Buffer */
|
||||
GTXE(SD_PWR_EN_PIN, 0x1)
|
||||
|
||||
/* Drive TX to zero */
|
||||
CTXS(SD_PWR_EN_PIN)
|
||||
}
|
||||
|
||||
Device (CARD)
|
||||
{
|
||||
Name (_ADR, 0x00000008)
|
||||
Method (_RMV, 0, NotSerialized)
|
||||
{
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
} /* Device (SDXC) */
|
||||
}
|
||||
81
src/soc/intel/elkhartlake/acpi/serialio.asl
Normal file
81
src/soc/intel/elkhartlake/acpi/serialio.asl
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Intel Serial IO Devices */
|
||||
|
||||
Device (I2C0)
|
||||
{
|
||||
Name (_ADR, 0x00150000)
|
||||
Name (_DDN, "Serial IO I2C Controller 0")
|
||||
}
|
||||
|
||||
Device (I2C1)
|
||||
{
|
||||
Name (_ADR, 0x00150001)
|
||||
Name (_DDN, "Serial IO I2C Controller 1")
|
||||
}
|
||||
|
||||
Device (I2C2)
|
||||
{
|
||||
Name (_ADR, 0x00150002)
|
||||
Name (_DDN, "Serial IO I2C Controller 2")
|
||||
}
|
||||
|
||||
Device (I2C3)
|
||||
{
|
||||
Name (_ADR, 0x00150003)
|
||||
Name (_DDN, "Serial IO I2C Controller 3")
|
||||
}
|
||||
|
||||
Device (I2C4)
|
||||
{
|
||||
Name (_ADR, 0x00190000)
|
||||
Name (_DDN, "Serial IO I2C Controller 4")
|
||||
}
|
||||
|
||||
Device (I2C5)
|
||||
{
|
||||
Name (_ADR, 0x00190001)
|
||||
Name (_DDN, "Serial IO I2C Controller 5")
|
||||
}
|
||||
|
||||
Device (SPI0)
|
||||
{
|
||||
Name (_ADR, 0x001e0002)
|
||||
Name (_DDN, "Serial IO SPI Controller 0")
|
||||
}
|
||||
|
||||
Device (SPI1)
|
||||
{
|
||||
Name (_ADR, 0x001e0003)
|
||||
Name (_DDN, "Serial IO SPI Controller 1")
|
||||
}
|
||||
|
||||
Device (SPI2)
|
||||
{
|
||||
Name (_ADR, 0x00120006)
|
||||
Name (_DDN, "Serial IO SPI Controller 2")
|
||||
}
|
||||
|
||||
Device (SPI3)
|
||||
{
|
||||
Name (_ADR, 0x00130000)
|
||||
Name (_DDN, "Serial IO SPI Controller 3")
|
||||
}
|
||||
|
||||
Device (UAR0)
|
||||
{
|
||||
Name (_ADR, 0x001e0000)
|
||||
Name (_DDN, "Serial IO UART Controller 0")
|
||||
}
|
||||
|
||||
Device (UAR1)
|
||||
{
|
||||
Name (_ADR, 0x001e0001)
|
||||
Name (_DDN, "Serial IO UART Controller 1")
|
||||
}
|
||||
|
||||
Device (UAR2)
|
||||
{
|
||||
Name (_ADR, 0x00190002)
|
||||
Name (_DDN, "Serial IO UART Controller 2")
|
||||
}
|
||||
8
src/soc/intel/elkhartlake/acpi/smbus.asl
Normal file
8
src/soc/intel/elkhartlake/acpi/smbus.asl
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Intel SMBus Controller 0:1f.4 */
|
||||
|
||||
Device (SBUS)
|
||||
{
|
||||
Name (_ADR, 0x001f0004)
|
||||
}
|
||||
45
src/soc/intel/elkhartlake/acpi/southbridge.asl
Normal file
45
src/soc/intel/elkhartlake/acpi/southbridge.asl
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <intelblocks/itss.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <soc/itss.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
/* PCI IRQ assignment */
|
||||
#include "pci_irqs.asl"
|
||||
|
||||
/* PCR access */
|
||||
#include <soc/intel/common/acpi/pcr.asl>
|
||||
|
||||
/* GPIO controller */
|
||||
#include "gpio.asl"
|
||||
|
||||
/* ESPI 0:1f.0 */
|
||||
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
|
||||
|
||||
/* PCH HDA */
|
||||
#include "pch_hda.asl"
|
||||
|
||||
/* PCIE Ports */
|
||||
#include "pcie.asl"
|
||||
|
||||
/* pmc 0:1f.2 */
|
||||
#include "pmc.asl"
|
||||
|
||||
/* Serial IO */
|
||||
#include "serialio.asl"
|
||||
|
||||
/* SMBus 0:1f.4 */
|
||||
#include "smbus.asl"
|
||||
|
||||
/* USB XHCI 0:14.0 */
|
||||
#include "xhci.asl"
|
||||
|
||||
/* PCI _OSC */
|
||||
#include <soc/intel/common/acpi/pci_osc.asl>
|
||||
|
||||
/* PMC Core*/
|
||||
#include <soc/intel/common/block/acpi/acpi/pmc.asl>
|
||||
|
||||
/* EMMC/SD card */
|
||||
#include "scs.asl"
|
||||
50
src/soc/intel/elkhartlake/acpi/xhci.asl
Normal file
50
src/soc/intel/elkhartlake/acpi/xhci.asl
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpe.h>
|
||||
|
||||
/* XHCI Controller 0:14.0 */
|
||||
|
||||
Device (XHCI)
|
||||
{
|
||||
Name (_ADR, 0x00140000)
|
||||
|
||||
Name (_PRW, Package () { GPE0_PME_B0, 3 })
|
||||
|
||||
Name (_S3D, 3) /* D3 supported in S3 */
|
||||
Name (_S0W, 3) /* D3 can wake device in S0 */
|
||||
Name (_S3W, 3) /* D3 can wake system from S3 */
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/* Root Hub for Elkhartlake PCH */
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 9) }
|
||||
Device (SS02) { Name (_ADR, 10) }
|
||||
Device (SS03) { Name (_ADR, 11) }
|
||||
Device (SS04) { Name (_ADR, 12) }
|
||||
Device (SS05) { Name (_ADR, 13) }
|
||||
Device (SS06) { Name (_ADR, 14) }
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue