From 70a815a1e0e5cad76c82be950b195a2adc1c6d3a Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Thu, 17 Jun 2021 11:39:48 -0700
Subject: [PATCH] mb/intel/adlrvp_m: Enable SaGv support

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/adlrvp/devicetree_m.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index b29533662e..ac80caff6b 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -35,6 +35,9 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
 
+	# Sagv Configuration
+	register "SaGv" = "SaGv_Enabled"
+
 	# Enable CNVi Bluetooth
 	register "CnviBtCore" = "true"