nb/intel/i945: Fix errors found by checkpatch.pl
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
219daafa8f
commit
70a8e34853
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@ -34,7 +34,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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u32 pciexbar_reg;
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int max_buses;
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dev = dev_find_slot(0, PCI_DEVFN(0,0));
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!dev)
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return current;
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@ -20,5 +20,5 @@ static void bootblock_northbridge_init(void)
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* 4GiB.
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*/
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
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pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
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}
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@ -26,7 +26,7 @@ void print_pci_devices(void)
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pci_devfn_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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dev += PCI_DEV(0, 0, 1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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@ -36,11 +36,11 @@ void print_pci_devices(void)
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}
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
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(dev >> 15) & 0x1f, (dev >> 12) & 7);
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printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
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printk(BIOS_DEBUG, " [%04x:%04x]\n", id & 0xffff, id >> 16);
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}
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}
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void dump_pci_device(unsigned dev)
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void dump_pci_device(unsigned int dev)
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{
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int i;
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@ -48,14 +48,12 @@ void dump_pci_device(unsigned dev)
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for (i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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if ((i & 0x0f) == 0)
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printk(BIOS_DEBUG, "%02x:", i);
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}
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val = pci_read_config8(dev, i);
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printk(BIOS_DEBUG, " %02x", val);
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if ((i & 0x0f) == 0x0f) {
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if ((i & 0x0f) == 0x0f)
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printk(BIOS_DEBUG, "\n");
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}
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}
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}
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@ -64,7 +62,7 @@ void dump_pci_devices(void)
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pci_devfn_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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dev += PCI_DEV(0, 0, 1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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@ -78,7 +76,7 @@ void dump_pci_devices(void)
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void dump_spd_registers(void)
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{
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unsigned device;
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unsigned int device;
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device = DIMM0;
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while (device <= DIMM3) {
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int status = 0;
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@ -86,14 +84,12 @@ void dump_spd_registers(void)
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printk(BIOS_DEBUG, "\ndimm %02x", device);
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for (i = 0; (i < 256); i++) {
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if ((i % 16) == 0) {
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if ((i % 16) == 0)
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printk(BIOS_DEBUG, "\n%02x: ", i);
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}
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status = smbus_read_byte(device, i);
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if (status < 0) {
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if (status < 0)
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printk(BIOS_DEBUG, "bad device: %02x\n", -status);
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break;
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}
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printk(BIOS_DEBUG, "%02x ", status);
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}
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device++;
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@ -101,14 +97,13 @@ void dump_spd_registers(void)
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}
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}
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void dump_mem(unsigned start, unsigned end)
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void dump_mem(unsigned int start, unsigned int end)
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{
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unsigned i;
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unsigned int i;
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printk(BIOS_DEBUG, "dump_mem:");
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for (i = start; i < end; i++) {
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if ((i & 0xf)==0) {
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if ((i & 0xf) == 0)
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printk(BIOS_DEBUG, "\n%08x:", i);
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}
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printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
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}
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printk(BIOS_DEBUG, "\n");
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@ -160,10 +160,10 @@ static void i945_setup_bars(void)
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pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
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setup_pch_gpios(&mainboard_gpio_map);
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printk(BIOS_DEBUG, " done.\n");
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@ -253,7 +253,7 @@ static void i945_setup_egress_port(void)
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EPBAR32(EPVC1RCAP) = reg32;
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if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
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if ((MCHBAR32(CLKCFG) & 7) == 0){ /* 1067MHz */
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if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */
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EPBAR32(EPVC1IST + 0) = 0x01380138;
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EPBAR32(EPVC1IST + 4) = 0x01380138;
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}
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@ -275,9 +275,8 @@ static void i945_setup_egress_port(void)
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}
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/* Is internal graphics enabled? */
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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MCHBAR32(MMARB1) |= (1 << 17);
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}
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/* Assign Virtual Channel ID 1 to VC1 */
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reg32 = EPBAR32(EPVC1RCTL);
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@ -305,7 +304,8 @@ static void i945_setup_egress_port(void)
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printk(BIOS_DEBUG, "Loading port arbitration table ...");
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/* Loop until bit 0 becomes 0 */
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timeout = 0x7fffff;
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while ((EPBAR16(EPVC1RSTS) & 1) && --timeout);
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while ((EPBAR16(EPVC1RSTS) & 1) && --timeout)
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;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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else
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@ -317,7 +317,8 @@ static void i945_setup_egress_port(void)
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printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
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/* Wait for VC1 negotiation pending */
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timeout = 0x7fff;
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while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout);
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while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout)
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;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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else
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@ -355,7 +356,7 @@ static void ich7_setup_dmi_rcrb(void)
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pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
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reg32 = RCBA32(V1CTL);
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reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) );
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reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24));
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reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
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RCBA32(V1CTL) = reg32;
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@ -410,7 +411,8 @@ static void i945_setup_dmi_rcrb(void)
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printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
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/* Wait for VC1 negotiation pending */
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timeout = 0x7ffff;
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while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout);
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while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout)
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;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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else
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@ -436,9 +438,8 @@ static void i945_setup_dmi_rcrb(void)
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DMIBAR32(DMICC) = reg32;
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if (activate_aspm) {
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if (activate_aspm)
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DMIBAR32(DMILCTL) |= (3 << 0);
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}
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#endif
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/* Last but not least, some additional steps */
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@ -510,7 +511,8 @@ static void i945_setup_dmi_rcrb(void)
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/* wait for bit toggle to 0 */
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printk(BIOS_DEBUG, "Waiting for DMI hardware...");
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timeout = 0x7fffff;
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while ((DMIBAR8(0x32) & (1 << 1)) && --timeout);
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while ((DMIBAR8(0x32) & (1 << 1)) && --timeout)
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;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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else
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@ -576,9 +578,8 @@ static void i945_setup_pci_express_x16(void)
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
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printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
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if (!(reg16 & 0x48)) {
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if (!(reg16 & 0x48))
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goto disable_pciexpress_x16_link;
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}
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reg16 |= (1 << 4) | (1 << 0);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
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@ -591,7 +592,7 @@ static void i945_setup_pci_express_x16(void)
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reg32 &= ~(1 << 8);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
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MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
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MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0));
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/* Initialize PEG_CAP */
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
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@ -613,7 +614,9 @@ static void i945_setup_pci_express_x16(void)
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/* Wait for training to succeed */
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
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&& --timeout)
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;
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reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
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if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
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@ -626,7 +629,7 @@ static void i945_setup_pci_express_x16(void)
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
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reg32 &= ~(0xf << 1);
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reg32 |=1;
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reg32 |= 1;
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pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
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@ -638,7 +641,9 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
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&& --timeout)
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;
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reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
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if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
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@ -659,15 +664,14 @@ static void i945_setup_pci_express_x16(void)
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
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reg32 &= 0xfffffc00; /* clear [9:0] */
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if (reg16 == 1) {
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if (reg16 == 1)
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reg32 |= 0x32b;
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// TODO
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/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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} else if (reg16 == 16) {
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else if (reg16 == 16)
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reg32 |= 0x0f4;
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// TODO
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/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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}
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reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
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printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
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@ -749,11 +753,10 @@ static void i945_setup_pci_express_x16(void)
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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if (i945_silicon_revision() >= 2) {
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if (i945_silicon_revision() >= 2)
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reg32 |= (1 << 12);
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} else {
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else
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reg32 &= ~(1 << 12);
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}
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
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@ -780,7 +783,7 @@ static void i945_setup_pci_express_x16(void)
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}
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}
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if (i945_silicon_revision() <= 2 ) {
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if (i945_silicon_revision() <= 2) {
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/* Set voltage specific parameters */
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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reg32 &= (0xf << 4); /* Default case 1.05V */
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@ -813,7 +816,8 @@ disable_pciexpress_x16_link:
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printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
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timeout = 0x7fffff;
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for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
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(reg32 & 0x000f0000) && --timeout;);
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(reg32 & 0x000f0000) && --timeout;)
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;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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else
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@ -193,7 +193,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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}
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if (smallest_err == 0xffffffff) {
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printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
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printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return -1;
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}
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@ -314,14 +314,14 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS
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| PANEL_POWER_ON | PANEL_POWER_RESET);
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printk (BIOS_DEBUG, "waiting for panel powerup\n");
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printk(BIOS_DEBUG, "waiting for panel powerup\n");
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while (1) {
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u32 reg32;
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reg32 = read32(mmiobase + PP_STATUS);
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if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
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break;
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}
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printk (BIOS_DEBUG, "panel powered up\n");
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printk(BIOS_DEBUG, "panel powered up\n");
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write32(mmiobase + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
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@ -346,8 +346,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
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}
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for (i = 0; i < (uma_size - 256) / 4; i++)
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{
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for (i = 0; i < (uma_size - 256) / 4; i++) {
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outl((i << 2) | 1, piobase);
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outl(pphysbase + (i << 12) + 1, piobase + 4);
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}
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@ -486,7 +485,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
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write32(mmiobase + PF_WIN_POS(0), 0);
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write32(mmiobase + PIPESRC(0), (639 << 16) | 399);
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write32(mmiobase + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
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write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
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write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(mmiobase + PFIT_CONTROL, 0x0);
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@ -526,8 +525,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
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printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
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}
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for (i = 0; i < (uma_size - 256) / 4; i++)
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{
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for (i = 0; i < (uma_size - 256) / 4; i++) {
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outl((i << 2) | 1, piobase);
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outl(pphysbase + (i << 12) + 1, piobase + 4);
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}
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@ -634,7 +632,8 @@ static void gma_func0_init(struct device *dev)
|
|||
udelay(50);
|
||||
pci_write_config8(dev, GDRST, 0);
|
||||
/* wait for device to finish */
|
||||
while (pci_read_config8(dev, GDRST) & 1) { };
|
||||
while (pci_read_config8(dev, GDRST) & 1)
|
||||
;
|
||||
|
||||
/* IGD needs to be Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
|
|
@ -721,7 +720,8 @@ static void gma_func1_init(struct device *dev)
|
|||
pci_write_config8(dev, 0xf4, 0xff);
|
||||
}
|
||||
|
||||
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
static void gma_set_subsystem(device_t dev, unsigned int vendor,
|
||||
unsigned int device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
|
|
@ -735,23 +735,20 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
|||
const struct i915_gpu_controller_info *
|
||||
intel_gma_get_controller_info(void)
|
||||
{
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
|
||||
if (!dev) {
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
|
||||
if (!dev)
|
||||
return NULL;
|
||||
}
|
||||
struct northbridge_intel_i945_config *chip = dev->chip_info;
|
||||
if (!chip) {
|
||||
if (!chip)
|
||||
return NULL;
|
||||
}
|
||||
return &chip->gfx;
|
||||
}
|
||||
|
||||
static void gma_ssdt(device_t device)
|
||||
{
|
||||
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
|
||||
if (!gfx) {
|
||||
if (!gfx)
|
||||
return;
|
||||
}
|
||||
|
||||
drivers_intel_gma_displays_ssdt_generate(gfx);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@
|
|||
#define DEVEN_D2F1 (1 << 4)
|
||||
|
||||
#ifndef BOARD_DEVEN
|
||||
#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
|
||||
#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1)
|
||||
#endif /* BOARD_DEVEN */
|
||||
|
||||
#define PAM0 0x90
|
||||
|
|
@ -99,9 +99,9 @@
|
|||
* MCHBAR
|
||||
*/
|
||||
|
||||
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
|
||||
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
|
||||
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
|
||||
|
||||
/* Chipset Control Registers */
|
||||
#define FSBPMC3 0x40 /* 32bit */
|
||||
|
|
@ -283,9 +283,9 @@
|
|||
* EPBAR - Egress Port Root Complex Register Block
|
||||
*/
|
||||
|
||||
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
|
||||
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
|
||||
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
|
||||
|
||||
#define EPPVCCAP1 0x004 /* 32bit */
|
||||
#define EPPVCCAP2 0x008 /* 32bit */
|
||||
|
|
@ -314,9 +314,9 @@
|
|||
* DMIBAR
|
||||
*/
|
||||
|
||||
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
|
||||
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
|
||||
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
|
||||
|
||||
#define DMIVCECH 0x000 /* 32bit */
|
||||
#define DMIPVCCAP1 0x004 /* 32bit */
|
||||
|
|
@ -359,10 +359,10 @@ void setup_ich7_gpios(void);
|
|||
|
||||
/* debugging functions */
|
||||
void print_pci_devices(void);
|
||||
void dump_pci_device(unsigned dev);
|
||||
void dump_pci_device(unsigned int dev);
|
||||
void dump_pci_devices(void);
|
||||
void dump_spd_registers(void);
|
||||
void dump_mem(unsigned start, unsigned end);
|
||||
void dump_mem(unsigned int start, unsigned int end);
|
||||
|
||||
u32 decode_igd_memory_size(u32 gms);
|
||||
|
||||
|
|
|
|||
|
|
@ -163,7 +163,8 @@ static void mc_read_resources(device_t dev)
|
|||
}
|
||||
}
|
||||
|
||||
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
static void intel_set_subsystem(device_t dev, unsigned int vendor,
|
||||
unsigned int device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
|
|
@ -214,11 +215,10 @@ static struct device_operations cpu_bus_ops = {
|
|||
static void enable_dev(device_t dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN)
|
||||
dev->ops = &pci_domain_ops;
|
||||
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_intel_i945_ops = {
|
||||
|
|
|
|||
|
|
@ -29,15 +29,14 @@ static uintptr_t smm_region_start(void)
|
|||
{
|
||||
uintptr_t tom;
|
||||
|
||||
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
|
||||
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
|
||||
/* IGD enabled, get top of Memory from BSM register */
|
||||
tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
|
||||
} else {
|
||||
tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
|
||||
}
|
||||
tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
|
||||
else
|
||||
tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
|
||||
|
||||
/* if TSEG enabled subtract size */
|
||||
switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
|
||||
switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
|
||||
case 0x01:
|
||||
/* 1MB TSEG */
|
||||
tom -= 0x100000;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -33,11 +33,10 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
|
|||
addr = 0;
|
||||
|
||||
if (channel_offset != 0) { /* must be dual channel */
|
||||
if (sysinfo->interleaved == 1) {
|
||||
if (sysinfo->interleaved == 1)
|
||||
addr |= (1 << 6);
|
||||
} else {
|
||||
else
|
||||
addr = ((u32)MCHBAR8(C0DRB3)) << 25;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < 28; i++) {
|
||||
|
|
@ -46,9 +45,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
|
|||
}
|
||||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
if (channel_offset == 0) {
|
||||
if (channel_offset == 0)
|
||||
reg32 = reg32 << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* [19] = 1: all bits are high
|
||||
|
|
@ -99,7 +97,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
|
|||
|
||||
}
|
||||
|
||||
static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
||||
static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
|
||||
{
|
||||
printk(BIOS_SPEW, " normalize()\n");
|
||||
|
||||
|
|
@ -122,7 +120,7 @@ static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int find_preamble(int channel_offset, u8 * mediumcoarse,
|
||||
static int find_preamble(int channel_offset, u8 *mediumcoarse,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
/* find start of the data phase */
|
||||
|
|
@ -156,7 +154,7 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
|
|||
* add a quarter clock to the current receive enable settings
|
||||
*/
|
||||
|
||||
static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
||||
static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine)
|
||||
{
|
||||
printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
|
||||
*mediumcoarse, *fine);
|
||||
|
|
@ -180,7 +178,7 @@ static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
||||
static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
u32 rcvenmt;
|
||||
|
|
@ -214,7 +212,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
||||
static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
|
||||
|
|
@ -313,9 +311,8 @@ static int receive_enable_autoconfig(int channel_offset,
|
|||
/* This is a debug check to see if the rcven code is fully working.
|
||||
* It can be removed when the output message is not printed anymore
|
||||
*/
|
||||
if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
|
||||
if (MCHBAR8(C0WL0REOST + channel_offset) == 0)
|
||||
printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,9 +65,8 @@ void udelay(u32 us)
|
|||
|
||||
tsc1 = rdtsc();
|
||||
dword = tsc1.lo + tscd.lo;
|
||||
if ((dword < tsc1.lo) || (dword < tscd.lo)) {
|
||||
if ((dword < tsc1.lo) || (dword < tscd.lo))
|
||||
tsc1.hi++;
|
||||
}
|
||||
tsc1.lo = dword;
|
||||
tsc1.hi += tscd.hi;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue