GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Various cosmetic fixes and improvements (trivial). 

- Use 'static' where appropriate.
 - Use 'const' where appropriate.
 - Indentation fixes.
 - Add comment wrt init code which is only valid for VT8237R.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-11-15 15:52:42 +00:00
parent e13abe53b4
commit 70ab323ae6
12 changed files with 99 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/southbridge/via/k8t890/k8t890_ctrl.c
View File

@ -41,12 +41,17 @@
* V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
* V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
*/
static void ctrl_init(struct device *dev)
static void ctrl_init_vt8237r(struct device *dev)
{
u8 reg;
/*
* This init code is valid only for the VT8237R! For different
* sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
* and VT8251) a different init code is required.
*/
device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
if (!devsb)
return;
@ -132,12 +137,12 @@ static void ctrl_enable(struct device *dev)
pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
}
static struct device_operations ctrl_ops = {
static const struct device_operations ctrl_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = ctrl_enable,
.init = ctrl_init,
.init = ctrl_init_vt8237r,
.ops_pci = 0,
};

3
src/southbridge/via/k8t890/k8t890_dram.c
View File

@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
@ -63,7 +62,7 @@ static void dram_enable(struct device *dev)
pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
}
static struct device_operations dram_ops = {
static const struct device_operations dram_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,

2
src/southbridge/via/k8t890/k8t890_host.c
View File

@ -30,7 +30,7 @@ static void host_enable(struct device *dev)
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
}
static struct device_operations host_ops = {
static const struct device_operations host_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,

2
src/southbridge/via/k8t890/k8t890_host_ctrl.c
View File

@ -78,7 +78,7 @@ static void host_ctrl_enable(struct device *dev)
dump_south(dev);
}
static struct device_operations host_ctrl_ops = {
static const struct device_operations host_ctrl_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,

9
src/southbridge/via/k8t890/k8t890_pcie.c
View File

@ -21,10 +21,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
void peg_init(struct device *dev)
static void peg_init(struct device *dev)
{
u8 reg;
@ -78,7 +77,7 @@ void peg_init(struct device *dev)
dump_south(dev);
}
void pcie_init(struct device *dev)
static void pcie_init(struct device *dev)
{
u8 reg;
@ -113,7 +112,7 @@ void pcie_init(struct device *dev)
dump_south(dev);
}
static struct device_operations peg_ops = {
static const struct device_operations peg_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
@ -123,7 +122,7 @@ static struct device_operations peg_ops = {
.ops_pci = 0,
};
static struct device_operations pcie_ops = {
static const struct device_operations pcie_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,

6
src/southbridge/via/k8t890/k8t890_traf_ctrl.c
View File

@ -19,13 +19,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include "k8t890.h"
void mmconfig_set_resources(device_t dev)
static void mmconfig_set_resources(device_t dev)
{
struct resource *resource;
u8 reg;
@ -106,7 +104,7 @@ static void traf_ctrl_enable(struct device *dev)
apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
}
static struct device_operations traf_ctrl_ops = {
static const struct device_operations traf_ctrl_ops = {
.read_resources = apic_mmconfig_read_resources,
.set_resources = mmconfig_set_resources,
.enable_resources = pci_dev_enable_resources,

1
src/southbridge/via/vt8237r/vt8237r.c
View File

@ -20,7 +20,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/keyboard.h>
#include "chip.h"

1
src/southbridge/via/vt8237r/vt8237r_bridge.c
View File

@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>

1
src/southbridge/via/vt8237r/vt8237r_ide.c
View File

@ -21,7 +21,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include "vt8237r.h"

9
src/southbridge/via/vt8237r/vt8237r_lpc.c
View File

@ -23,7 +23,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
@ -48,7 +47,7 @@
extern void dump_south(device_t dev);
struct ioapicreg {
static struct ioapicreg {
u32 reg;
u32 value_low;
u32 value_high;
@ -146,7 +145,7 @@ static void pci_routing_fixup(struct device *dev)
* Set up the power management capabilities directly into ACPI mode.
* This avoids having to handle any System Management Interrupts (SMIs).
*/
void setup_pm(device_t dev)
static void setup_pm(device_t dev)
{
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
@ -299,7 +298,7 @@ static void vt8237r_init(struct device *dev)
rtc_init(0);
}
void vt8237r_read_resources(device_t dev)
static void vt8237r_read_resources(device_t dev)
{
struct resource *res;
@ -320,7 +319,7 @@ void vt8237r_read_resources(device_t dev)
* than standard PC I/O addresses), however it does control the ISA bus
* and so we need to manually call enable childrens resources on that bus.
*/
void vt8237r_enable_resources(device_t dev)
static void vt8237r_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);

1
src/southbridge/via/vt8237r/vt8237r_sata.c
View File

@ -20,7 +20,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#define SATA_MISC_CTRL 0x45