lib/romstage_stack.c: Remove unused functions

Change-Id: I1e66ff3fe7462dfeae2a7ce7e3a8083cf90a15f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33936
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-07-01 12:19:48 +02:00 committed by Kyösti Mälkki
parent 6e2d0c1b90
commit 70b421f3bd
2 changed files with 0 additions and 19 deletions

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@ -176,8 +176,6 @@ void run_ramstage(void);
/* Determine where stack for ramstage loader is located. */ /* Determine where stack for ramstage loader is located. */
enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM };
uintptr_t romstage_ram_stack_base(size_t size, int src); uintptr_t romstage_ram_stack_base(size_t size, int src);
uintptr_t romstage_ram_stack_top(void);
uintptr_t romstage_ram_stack_bottom(void);
/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, /* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path,
* if ramstage overwrites low memory. */ * if ramstage overwrites low memory. */

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@ -32,20 +32,3 @@ uintptr_t romstage_ram_stack_base(size_t size, int src)
return CONFIG_RAMTOP - size; return CONFIG_RAMTOP - size;
return 0; return 0;
} }
uintptr_t romstage_ram_stack_bottom(void)
{
return romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
ROMSTAGE_STACK_CBMEM);
}
uintptr_t romstage_ram_stack_top(void)
{
uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
ROMSTAGE_STACK_CBMEM);
stack_top += ROMSTAGE_RAM_STACK_SIZE;
/* Make it aligned to a 8-byte boundary. */
stack_top = ALIGN_DOWN(stack_top, 8);
return stack_top;
}