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mb/google/reef: Override USB2 phy settings 

Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.

port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

BUG=b:72623892
BRANCH=master
TEST=emerge-reef coreboot chromeos-bootimage

Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/23878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Chen 2018-02-27 19:42:46 +08:00 committed by Martin Roth
parent 06e3e1f055
commit 70ba1b7e78
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -116,6 +116,22 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 4,
.Usb20PerPortTxiSet = 4,
.Usb20IUsbTxEmphasisEn = 1,
.Usb20PerPortTxPeHalf = 0,
}"
# Override USB2 PER PORT register (PORT 4)
register "usb2eye[4]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 7,
.Usb20IUsbTxEmphasisEn = 1,
.Usb20PerPortTxPeHalf = 0,
}"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF