soc/intel/meteorlake: Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB

On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by
P2SB on IOE/SOC die.
So this patch does:
1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
2. Include pcie_clk.asl
3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H.

BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled.

Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/meteorlake/Kconfig

@@ -63,6 +63,7 @@ config CPU_SPECIFIC_OPTIONS
 	select MP_SERVICES_PPI_V2
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP_AP_WORK
+	select PCIE_CLOCK_CONTROL_THROUGH_P2SB
 	select PLATFORM_USES_FSP2_3
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
@@ -424,4 +425,8 @@ config PCIE_LTR_MAX_NO_SNOOP_LATENCY
 	help
 	  Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms.
 
+config IOE_DIE_CLOCK_START
+	int
+	default 6 if SOC_INTEL_METEORLAKE_U_H
+
 endif

src/soc/intel/meteorlake/acpi/southbridge.asl

@@ -12,6 +12,9 @@
 #include <soc/intel/common/acpi/ioe_pcr.asl>
 #endif
 
+/* PCIE src clock control */
+#include <soc/intel/common/acpi/pcie_clk.asl>
+
 /* PCH clock */
 #include "camera_clock_ctl.asl"