mb/google/rex: Optimize FMD usage for rex variants
This patch eliminates the need to maintain separate FMD files for rex variants and rex variants with ISH. It does this by using the BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW layout sizes. TEST=Able to build and boot google/rex and google/rex_ec_ish. Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -120,8 +120,6 @@ config DEVICETREE
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
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config FMDFILE
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish-debug-fsp.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH && BUILDING_WITH_DEBUG_FSP
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
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@ -8,7 +8,11 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_A(CBFS) 4500K
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#else
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ME_RW_A(CBFS) 4400K
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ME_RW_A(CBFS) 4400K
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#endif
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}
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}
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# This section starts at the 16M boundary in SPI flash.
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# MTL does not support a region crossing this boundary,
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@ -18,7 +22,11 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_B(CBFS) 4500K
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#else
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ME_RW_B(CBFS) 4400K
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ME_RW_B(CBFS) 4400K
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#endif
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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@ -8,7 +8,11 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_A(CBFS) 4500K
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#else
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ME_RW_A(CBFS) 4400K
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ME_RW_A(CBFS) 4400K
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#endif
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}
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}
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# This section starts at the 16M boundary in SPI flash.
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# MTL does not support a region crossing this boundary,
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@ -18,7 +22,11 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_B(CBFS) 4500K
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#else
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ME_RW_B(CBFS) 4400K
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ME_RW_B(CBFS) 4400K
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#endif
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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@ -1,56 +0,0 @@
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FLASH 32M {
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SI_ALL 9M {
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SI_DESC 16K
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SI_ME
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}
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SI_BIOS 23M {
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RW_SECTION_A 7680K {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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ME_RW_A(CBFS) 4500K
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}
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# because the SPI flash is memory-mapped into two non-
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# contiguous windows.
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RW_SECTION_B 7680K {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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ME_RW_B(CBFS) 4500K
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}
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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RW_ELOG(PRESERVE) 16K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
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# It is placed in the common `chromeos.fmd` file because it is only 4K and there
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# is free space in the RW_MISC region that cannot be easily reclaimed because
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# the RW_SECTION_B must start on the 16M boundary.
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RW_SPD_CACHE(PRESERVE) 4K
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 24K
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}
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RW_LEGACY(CBFS) 1M
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RW_UNUSED 2M
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 4M {
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RO_VPD(PRESERVE) 16K
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RO_GSCVD 8K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 12K
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COREBOOT(CBFS)
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}
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}
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}
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}
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@ -1,56 +0,0 @@
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FLASH 32M {
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SI_ALL 9M {
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SI_DESC 16K
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SI_ME
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}
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SI_BIOS 23M {
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RW_SECTION_A 7M {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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ME_RW_A(CBFS) 4500K
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}
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# because the SPI flash is memory-mapped into two non-
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# contiguous windows.
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RW_SECTION_B 7M {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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ME_RW_B(CBFS) 4500K
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}
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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RW_ELOG(PRESERVE) 16K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
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# It is placed in the common `chromeos.fmd` file because it is only 4K and there
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# is free space in the RW_MISC region that cannot be easily reclaimed because
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# the RW_SECTION_B must start on the 16M boundary.
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RW_SPD_CACHE(PRESERVE) 4K
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 24K
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}
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RW_LEGACY(CBFS) 1M
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RW_UNUSED 3M
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 4M {
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RO_VPD(PRESERVE) 16K
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RO_GSCVD 8K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 12K
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COREBOOT(CBFS)
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}
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}
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}
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}
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