From 70d8baef921c50a49e055de3ed32cca618820c11 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 16:48:47 +0100 Subject: [PATCH] soc/intel/jasperlake: Drop unreferenced devicetree settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Michael Niewöhner --- src/soc/intel/jasperlake/chip.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 2fc32c9840..9d4bc5c80a 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -129,22 +129,13 @@ struct soc_intel_jasperlake_config { /* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh; - /* Integrated Sensor */ - uint8_t PchIshEnable; - - /* Heci related */ - uint8_t Heci3Enabled; - /* VR Config Settings for IA Core */ uint16_t ImonSlope; uint16_t ImonOffset; /* Gfx related */ - uint8_t IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan; - uint32_t GraphicsConfigPtr; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;